Specifications

CHAPTER 6: BLOCK-BASED DESIGN

USING LOGICLOCK REGIONS IN TOP-DOWN INCREMENTAL COMPILATION FLOWS

ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 119

Using LogicLock Regions in Top-

Down Incremental Compilation

Flows

If you are planning to perform a full incremental compilation, it is important

to assign design partitions to physical locations on the device. You can

assign design partitions to LogicLock regions by dragging a design partition

from the Hierarchy tab of the Project Navigator window, the Design

Partitions window, or the Node Finder and dropping it directly in the

LogicLock Regions window or to a LogicLock region in the Timing Closure

floorplan.

Altera recommends that you create one LogicLock region for each partition

in your design. The best performance can generally be achieved when these

regions are all fixed-size, fixed-location regions. Ideally, you should assign

the LogicLock regions manually to specific physical locations in the device

by using the Timing Closure floorplan; however, you can also allow the

Quartus II software to assign LogicLock regions to physical locations

somewhat automatically by setting the LogicLock region Size option to

Auto and the State option to Floating. If the partition has many memory or

DSP blocks, it is recommended you exclude them from the LogicLock

region. After the initial compilation, you should back-annotate the

LogicLock region properties (not the nodes) to ensure that all the LogicLock

regions have a fixed size and a fixed location. This process will create initial

floorplan assignments that can be modified more easily, as needed.

For Information About Refer To

Using LogicLock with the Quartus II

software

“LogicLock Design Methodology,” in the

Quartus II Handbook, vol. 2, on the Altera

web site

“Overview: Using LogicLock Regions” in

Quartus II Help

The LogicLock module in the Quartus II

Tutorial