Specifications

CHAPTER 5: PLACE & ROUTE
OPTIMIZING THE FIT
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 99
page of the Settings dialog box (Assignments menu) allows you to specify
which design reliability guidelines to use when checking your design. For
more information, refer to “Using the Design Assistant to Check
Design Reliability” on page 79 in Chapter 4, “Synthesis.”
Optimizing the Fit
Once you have run the Fitter and have analyzed the results, you can try
several options to optimize the fit:
■ Using location assignments
■ Setting options that control place and route
■ Using the Resource Optimization Advisor
■ Using the Design Space Explorer
Using Location Assignments
You can assign logic to physical resources on the device, such as a pin, logic
cell, or Logic Array Block (LAB), by using the Timing Closure floorplan or
the Assignment Editor in order to control place and route. You may want to
use the Timing Closure floorplan to edit assignments because it gives you a
graphical view of the device and its features. If you want to create new
location assignments, you may want to use the Assignment Editor
command (Assignments menu), which allows you to create several node-
specific assignments at once. In addition to using the Timing Closure
floorplan or Assignment Editor to create assignments, you can also use Tcl
commands. If you want to specify global assignments for the project, you
can use the Settings dialog box (Assignments menu). For more information
about specifying initial design constraints, refer to “Chapter 3: Constraint
Entry” on page 55.
Once you create an assignment, you can edit it in the Assignment Editor or
the Timing Closure floorplan. After compilation, you can use the Timing
Closure floorplan to edit existing resource assignments to pins, logic cells,
rows, columns, regions, MegaLAB structures, and LABs. You can use the
Timing Closure floorplan, the LogicLock Regions window, or the LogicLock
Region Properties dialog box to assign nodes or entities to LogicLock
regions.