User`s guide

Static RAM
MWRlTE
Wait state generation
for memories slower
than 300 ns.
Bus load
Buffering
Phantcm:
Mirroring
Vector ZCB Single Board Carplter
Fully compatible
Jumper option to generate MWRITE on board
StaOOard: option enabled.
3 options: generate one wait state on each bus
cycle, generate one wait state after each Ml
instruction, generate no wait states.
StaOOard: generate one wait state after each Ml
instruction. .
1
staOOard Tl'L load on all inputs
Fan oot: 15 standard (60 low ~r shottky)
output buffer disable canpatible with Vector Graphic
EPRCM/RAM Boards, which generate phantan in resJ;OrlSe to
Fower-on-clear (POC). J1..IIIper selectable: on/off.
Standard: enabled
StaOOard: enabled, can be disabled.
SPEX:IFlCATICNS-I/O
Capacity 1 serial RS-232 and 3 8-bit parallel ports prograntnable
as input or ootput.
Serial port 1, using 8251 controller chip.
Port addresses Any increment of four fran OOH to FEll. Preset
addresses are: Da.ta, 04H (echoed on 06H);
Control, 05H (echoed on 07H.)
Signal levels EIA RS-232C
RS-232 handshaking Typical haOOshaking is provided, ie. Rl'S, ers, lJl'R,
Il3R, etc.
Asynchronoos
Rates
110-9600 baw (switch selectable)
Da.ta bits
5 - 8, prcgranunable
Step bits
1, 1 1/2, or 2, progranunable
parity
Even, odd, or none, progranunable
Rev.
I-a 6/11/80