Specifications

2000 Jun 26 9
Philips Semiconductors Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
varying input data rates from the inside-to-outside of the
disc.
In the lock-to-disc mode, the FIFO is blocked and the
decoder will adjust its output data rate to the disc speed.
Hence, the frequency of the I
2
S-bus (WCLK and SCLK)
clocks are dependent on the disc speed. In the lock-to-disc
mode there is a limit on the maximum variation in disc
speed that the SAA7327 will follow. Disc speeds must
always be within 25% to 100% range of their nominal
value. The lock-to-disc mode is enabled/disabled by
decoder register E.
7.1.4 STANDBY MODES
The SAA7327 may be placed in two standby modes
selected by decoder register B (it should be noted that the
device core is still active):
• Standby 1: ‘CD-STOP’ mode; most I/O functions are
switched off
• Standby 2: ‘CD-PAUSE’ mode; audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active; this is also
called a ‘Hot Pause’.
In the standby modes the various pins will have the
following values:
• MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset: operating in standby 2); put
in high-impedance, PDM mode (standby 1 and reset:
operating in standby 2)
• SCL and SDA: no interaction; normal operation
continues
• SCLK, WCLK, DATA, EF and DOBM: 3-state in both
standby modes; normal operation continues after reset
• CRIN, CROUT, CL16 and CL11/4: no interaction;
normal operation continues
• V1, V2/V3, V4, V5 and CFLG: no interaction; normal
operation continues.
Table 1 Playback speeds
Notes
1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is
available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).
2. Data capture performance is not optimized for this option.
REGISTER B SELPLL
CRYSTAL FREQUENCY (MHz) CL11
FREQUENCY
(MHz)
(1)33.8688 16.9344 8.4672
00XX 0 n = 1 −−11.2896
00XX 1 −−n = 1 11.2896
01XX 0 − n=1 − 5.6448
01XX 1 − n=1 − 11.2896
10XX 0 n = 2 −−11.2896
10XX 1 −−n = 2 11.2896
11XX 0 − n=2
(2)
− 5.6448
11XX 1 − n=2 − 11.2896