Specifications

2000 Jun 26 41
Philips Semiconductors Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
6
(motor output
configuration)
0110 XX00 motor power maximum 37% reset
XX01 motor power maximum 50% −
XX10 motor power maximum 75% −
XX11 motor power maximum 100% −
00XX MOTO1, MOTO2 pins 3-state reset
01XX motor PWM mode −
10XX motor PDM mode −
11XX motor CDV mode −
7
(DAC output
and status
control)
0111 XX00 interrupt signal from servo at STATUS pin reset
XX10 status bit from decoder status register at STATUS
pin
−
X0XX DAC data normal value reset
X1XX DAC data inverted value −
0XXX left channel first at DAC (WCLK normal) reset
1XXX right channel first at DAC (WCLK inverted) −
8
(PLL loop filter
bandwidth)
see Table 15 −
9
(PLL
equalization)
1001 0011 PLL loop filter equalization reset
0001 PLL 30 ns over-equalization −
0010 PLL 15 ns over-equalization −
0100 PLL 15 ns under-equalization −
0101 PLL 30 ns under-equalization −
A
(EBU output)
1010 XX0X EBU data before concealment −
XX1X EBU data after concealment and fade reset
X0X0 level II clock accuracy (<1000 ppm) reset
X0X1 level I clock accuracy (<50 ppm) −
X1X0 level III clock accuracy (>1000 ppm) −
X1X1 EBU off - output low −
0XXX flags in EBU off reset
1XXX flags in EBU on −
B
(speed control)
1011 X0XX 33.8688 MHz crystal present, or 8.4672 MHz (or
16.9344 MHz) crystal with SELPLL set HIGH
reset
X1XX 16.9344 MHz crystal present −
0XXX single-speed mode reset
1XXX double-speed mode −
XX00 standby 1: ‘CD-STOP’ mode reset
XX10 standby 2: ‘CD-PAUSE’ mode −
XX11 operating mode −
REGISTER ADDRESS DATA FUNCTION INITIAL
(1)