Specifications

2000 Jun 26 39
Philips Semiconductors Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
7.15.3 DECODER REGISTERS AND SHADOW REGISTERS
To maintain compatibility with the SAA737x series,
decoder registers 0 to F are identical to the SAA7370.
However, to control the extra functionality of SAA7327, a
new set of registers called shadow registers have been
implemented.
These are accessed by using the LSB of decoder
register F. This bit is called SHADEN (shadow registers
enable) on SAA7327. When this bit is set to logic 1 (i.e.
decoder register F set to XXX1), any subsequent
addresses will be decoded by the shadow registers.
In fact, only four addresses are implemented as shadow
registers; 3, 7, A and C. Any other addresses sent while
SHADEN = 1 are invalid and have no effect.
When SHADEN is set to logic 0 (decoder register F set to
XXX0) all subsequent addresses are decoded by the main
decoder registers again.
Access to decoder register F is always enabled so that
SHADEN can be set or reset as required.
The SHADEN bit and subsequent shadow registers are
programmed identically to the main decoder registers, i.e.
they can be directly programmed when using SAA7327 in
4-wire mode or programmed via the servo interface when
using 3-wire or I
2
C-bus modes.
The main decoder registers are shown in Table 14. The
functions implemented using shadow registers are shown
in Table 16.
7.15.4 SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F
Table 14 Registers 0 to F
REGISTER ADDRESS DATA FUNCTION INITIAL
(1)
0
(fade and
attenuation)
0000 0000 mute reset
0010 attenuate −
0001 full-scale −
0100 step down −
0101 step up −
1
(motor mode)
0001 X000 motor off mode reset
X001 motor stop mode 1 −
X010 motor stop mode 2 −
X011 motor start mode 1 −
X100 motor start mode 2 −
X101 motor jump mode −
X111 motor play mode −
X110 motor jump mode 1 −
1XXX anti-windup active −
0XXX anti-windup off reset