Specifications

2000 Jun 26 20
Philips Semiconductors Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
7.9 EBU interface
The bi-phase mark digital output signal at pin DOBM is in
accordance with the format defined by the IEC 958
specification. Three different modes can be selected via
decoder register A:
• DOBM pin held LOW
• Data taken before concealment, mute and fade (must
always be used for CD-ROM modes)
• Data taken after concealment, mute and fade.
7.9.1 FORMAT
The digital audio output consists of 32-bit words
(‘subframes’) transmitted in bi-phase mark code (two
transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384. The formats are
given in Table 6.
Table 6 Format
Table 7 Description of Table 6
Table 8 Bit assignment
FUNCTION BITS DESCRIPTION
Sync 0 to 3 −
Auxiliary 4 to 7 not used; normally zero
Error flags 4 CFLG error and interpolation flags when selected by register A
Audio sample 8 to 27 first 4 bits not used (always zero) twos complement LSB = bit 12,
MSB = bit 27
Validity flag 28 valid = logic 0
User data 29 used for subcode data (Q-to-W)
Channel status 30 control bits and category code
Parity bit 31 even parity for bits 4 to 30
FUNCTION DESCRIPTION
Sync The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.
Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample
(no block start) and sync W: word contains right sample.
Audio sample Left and right samples are transmitted alternately.
Validity flag Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This
flag remains the same even if data is taken after concealment.
User data Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.
Channel status The channel status bit is the same for left and right words. Therefore a block of 384 words contains
192 channel status bits. The category code is always CD. The bit assignment is given in Table 8.
FUNCTION BITS DESCRIPTION
Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis
Reserved mode 4 to 7 always zero
Category code 8 to 15 CD: bit 8 = logic 1, all other bits = logic 0
Clock accuracy 28 to 29 set by register A; 10 = level I; 00 = level II; 01 = level III
Remaining 6 to 27 and 30 to 191 always zero