Repair manual

2-46

THEORY OF OPERATION

F out

Counter

Amplifier/

Filter

Voltage

Controlled

Oscillator

Phase

Detector

Figure 2-4. Phase-Locked Loop Frequency Synthesizer Block Diagram

The phase-locked loop frequency synthesizer, when operating properly,

locks onto an input signal, tracks it in frequency, and outputs a fixed

phase signal relative to its input signal. The input frequency to the

phase-locked loop (Fin A) is crystal controlled. The output frequency

(Fout) is changed by varying the programmable divisor (/N). By stepping

N in integer increments, the output frequency is changed by a frequency

of Fin per increment.

The crystal controlled input frequency (Fin A) is outputted by the

internal timer of the microprocessor. Timer 1 output (TIMR1OUT) from

the microprocessor generates an output clock signal (XTALHS) that is

applied to the input of the Frequency Synthesizer circuit.

Upon command, this clock signal (XTALHS) is gated to the input of the

Frequency Synthesizer circuit. This gated input signal (PLLHS) is the

input frequency (Fin A) to the phase detector. Timer 1 output

(TIMR1OUT) from the microprocessor is programmed to provide a

crystal controlled 14.7 KHz Horizontal Sync (HSYNC) signal.

The output frequency from the Frequency Synthesizer circuit is used as

the base frequency thats generates the required timing by the video

circuit.

A derivitive of the clock signal from TIMR1OUT is the serial clock (SC)

and the Horizontal Timing Counter clock (PCLK).

The serial clock signal is used by the Video Read Address Memory

(VRAM’s). The horizontal timing clock clocks the Horizontal Timing

Counter. This counter is controlled by TIMTBL DMA transactions.

F in B

F in A