Repair manual

2-45
THEORY OF OPERATION
the /HLDA signal, is sent to the control PAL 1 (U45) to indicate that a
DRAM read cycle should occur. /HLDA is also sent to the control PAL 3
(U48) so that the time table offset is asserted on the Latched Address
Bus (LA9 - LA12). The /HLDA signal is also available to the RAM
control PAL’s so that the appropriate RAM address lines (RA) are
asserted. Notice that data bit 10 (AD10) and /HLDA2 are inputs to
control PAL 3 (U48). This is the ENDTABLE bit. The 4-bit counter
which is implemented in control PAL 3 is reset to zero when /HLDA2
and AD10 are asserted. When /HLDA2 is asserted and AD10 is false, the
4-bit counter increments.
d. Frequency Synthesizer
The horizontal resolution of the Digital Palette is programmable and
continuous from 256 pixels up to 2048 pixels (4096 pixels with the
additional VRAM and support circuitry).
The Frequency Synthesizer circuit (Figure 2-9, sheet 4) is used to
generate a base clock from which the pixel clock is derived. This
circuit has a tuning range of 2 to 1. Additional ranges are generated by
dividing the base clock by a factor of 2, 4, or 8. The range of the
Frequency Synthesizer circuit is 20 MHz to 40 MHz. Two low frequency
signals are applied to the input of the Frequency Synthesizer circuit.
The output of the Frequency Synthesizer circuit settles to a frequency
which locks the two inputs. One input is the crystal based Horizontal
Sync (HSYNC) signal which is generated by TIMER 1 of the
microprocessor. The other input is a Horizontal Sync (HSYNC) signal
which is generated by a programmable counter. This programmable
counter is clocked by a derivitive of the frequency synthesizer base clock,
thus providing a feedback loop.
Once the programmable counter is set to a specific count which is
dependent on the horizontal resolution and the Frequency Synthesizer has
locked the two inputs, the base clock becomes stable. This stable base
clock is used to generate all of the necessary signals for the video
section.
The Frequency Synthesizer circuit (Figure 2-9, sheet 4) generates a
continous and programmable horizontal image resolution from 512 pixels
to 2048 pixels (4096 pixels with additional, optional hardware). It uses a
phase-locked loop frequency synthesizer consisting of a phase detector,
an amplifier/filter, and a voltage-controlled oscillator. By adding a
divide-by-N counter in its feedback loop, a stable output frequency will
be generated from a relatively low input frequency. Figure 2-4 shows a
block diagram of the phase-locked loop frequency synthesizer.