Repair manual

2-44
THEORY OF OPERATION
b. Horizontal Timing Down Counter
The Horizontal Timing Down Counter (Figure 2-9, sheet 3) is a 9-bit
counter. It is driven by a clock which is one-half the frequency of the
output of the Frequency Synthesizer. The video PAL (VIDEP1) is
clocked by the output of the Frequency Synthesizer and has an output
called 20M. The Frequency Synthesizer output has a nominal frequency
range of 20 MHz to 40 MHz. The 20M signal has a nominal frequency
range of 10 MHz to 20 MHz. This nominal frequency range is the range
of frequencies when the Frequency Synthesizer is locked. As the
Frequency Synthesizer locks up, the frequency may run as high as 30%
higher which means that the 20M signal can be a frequency as high as
26 MHz. The Horizontal Down Counter, which provides the down count
function, has a maximum frequency specification of 20 MHz. Therefore,
the least significant bit of down counting is implemented in the HTIMP1
PAL. The upper 8-bits of the counter are implemented in the Horizontal
Timing Down Counter.
The 20M signal is fed as a clock input to the HTIMP2 PAL. This
HTIMP2 PAL performs a number of tasks related to the Horizontal
Timing Down Counter. First, it generates the clock (TCLK) for the down
counter. Second, it generates the counter load (TCLOAD) signal. Third,
it implements the least significant bit of the Horizontal Timing Down
Counter by skipping a TCLK cycle if the least significant bit is set.
c. TIMTBL DMA Transaction
When the Horizontal Timing Down Counter count expires, the /TRCO
signal is asserted. This causes two functions to occur. The counter value
from the previous DMA cycle is loaded into the Horizontal Timing Down
Counter and the control bits in the control input register are loaded into
the HTIMP2 PAL. The assertion of /TRCO signal also causes the
HTIMP3 PAL to assert the HOLD signal so that the next TIMTBL DMA
cycle can load the input registers.
When the microprocessor senses the HOLD signal, it completes the
current CPU cycle, tri-states the address/data bus, and asserts the HLDA
signal. The HTIMP3 PAL senses /HLDA signal and starts a DMA
transaction. Three of the registers in the HTIMP3 PAL serve as a state
machine for the DMA transaction. These three signals are /HLDA0,
/HLDA1, and /HLDA2.
Referring to the RAM Control section of the Horizontal Timing Down
Counter (Figure 2-9, sheet 4), the signal /HLDA1, asserted shortly after