Repair manual

2-43
THEORY OF OPERATION
Table 2-10. Significance of Address Segment Bits
Bit Line Function
AD15 HSYNC If this bit is true, the next time state will be an horizontal
sync (HSYNC) state. The HSYNC line will be asserted.
When the HSYNC line is asserted , bits AD11 through AD14 function as follows:
AD14 Not Used
AD13 DATAEN The data enable (DATAEN) line gets signals from the
video section.
AD12 Not Used
AD11 Not Used
When the HSYNC line is not asserted, bits AD11 through AD14 function as follows:
AD14 SCEN The shift clock enable (SCEN) line enables the VRAM SC
clock, allowing pixel data to be clocked out of the VRAM
shift registers.
AD13 VRSR2 VRSR2 and VRSR1 indicate which type of VRAM.
AD12 VRSR1 Cycle will occur on the next TIMTBL DMA
transfer.
AD11 Not Used
AD10 ENTABLE This bit indicates that the particular entry is last in the
offset table. The offset table is reset to zero.
AD9 DMA1REQ When this bit is true, it indicates that a DMA 1 request
should be generated. The microprocessor responds to this
request by executing the DMA 1 cycle.