Repair manual

2-42
THEORY OF OPERATION
a. Horizontal Sync and Video Timing Generation
The Horizontal Sync (HSYNC) and Video Enable signals are generated
by a background DMA process which loads a control register and down
counter from a table of data in memory. There are four major time states
which must be generated: the Horizontal Sync (HSYNC), back porch,
video enable, and front porch. For each of these time states, a distinct
DMA transfer occurs which loads the next time state that occurs into the
control register and the duration of that time state into the down counter.
The microprocessor clock and the base clock for video timing are
asynchronous. It requires a front end register for the control and counter
information. These registers are loaded by a DMA transfer. The control
and counter are loaded with the contents of the register when the previous
video time state expires (current counter value reaches zero).
The DMA transaction which occurs uses the HOLD/HLDA signals from
the microprocessor. The circuitry on the Logic Controller P.C. board
generates the necessary signals to perform the DMA transfer. This type
of transfer, referred to as a TIMTBL DMA, takes precedence over the
microprocessor’s internal DMA channels.
The circuitry on the Logic Controller P.C. board will read a word of data
from a table in low memory. This table resides at offset 0x03E0 (segment
address 0x3E) in memory and can be up to 16 words long. This location
was choosen so that it would not interfere with the DOS operating system.
A 4-bit counter in the RCTLP3 PAL generates the offset into the table.
After each DMA transfer, this counter is incremented. One of the control
bits in the table (ENDTABLE bit) signifies that this is the last entry in the
table. At the end of a DMA cycle, when this bit is set, the 4-bit counter is
reset to zero. The low 9 bits of the 16-bit word contains a count which is
loaded into a input-registered down counter. The upper 7 bits are control
bits which determine which time state occurs. Table 2-10 indicates the
significance of the bits.