Repair manual

2-41
THEORY OF OPERATION
the VDEFLCT signal is used to drive the vertical yoke of the CRT.
At the end of each horizontal scan line, the microprocessor network flags the
vertical deflection instructions from the EPROM. The EPROM applies the
specified vertical deflection instructions to the input of the microprocessor net
work via the Address/Data communications bus. The microprocessor network
decodes these instructions from the EPROM and then applies them via the
Address/Data communications to the octal latch in the Vertical Deflection circuit.
Specified data enable signals from the vertical deflect control PAL in the
Horizontal Timing Counter circuit (Figure 2-9, sheet 3) enables the octal latch
and thesample and hold network. The octal latch outputs the 8-bit vertical
deflection data to the digital-to-analog (D/A) converters. The D/A converters
process this 8-bit vertical deflection data into an analog signal. This analog signal
is then processed by the sample and hold network into a vertical deflection
(VDEFLECT) signal.
The sample and hold network, enabled by the vertical data enable (VDATAEN)
signal, applies the processed VDEFLECT signal via connector J9 to the input of
the Vertical Deflection processor on the Monitor P.C. Board. The vertical
Deflection processor generates the necessary vertical drive pulse that is capable of
directly driving the vertical yoke of the CRT. At the end of the exposure of a
RCTLP3 line, the CRT beam is deflected vertically one scan line.
6. Horizontal Signal Generation
During normal operation of the Digital Palette, timer 1 of the microprocessor
generates the Horizontal Sync (HSYNC) signal. This HSYNC signal is used to
clock the following:
o Feed back signal for the Frequency Synthesizer circuit (Figure 2-9, sheet 4).
o Horizontal Sync Driver Network (Figure 2-9, sheet 5).
o Input to one of the microprocessor’s internal timers (Figure 2-9, sheet 1).
This timer input allows the microprocessor to sense the stability of the
Frequency Synthesizer circuit. It also senses the time that it takes the output
of the Frequency Synthesizer circuit to lock onto the crystal controlled
Horizontal Sync (HSYNC) signal.
The fact that HSYNC signal is being generated indicates that the Horizontal
Timing Generator is operating.