Repair manual

2-39
THEORY OF OPERATION
signal. This VROE signal is asserted during a VRAM read and a VRAM
shift register load cycle. During the VRAM cycle, VROE is asserted after
the assertion of the VRAS signal. During a VRAM shift register cycle,
VROE is asserted before the assertion of the
VRAS signal.
The trigger control in the Horizontal Generation circuit generates the
TRGSYNC signal.
4. Video Generation
The Video Generation circuit (Figure 2-9, sheet 4) processes the parallel pixel
image data from VRAM into a serialized VIDEO signal that is applied via
connector J9 to the input of the Cathode Driver network on the Monitor P.C.
Board. It is then applied to the cathode of the CRT. Refer to paragraph E in this
Section of the Service Manual for a functional description of how the VIDEO
signal turns on the CRT.
When an exposure sequence (Start Exposure, Parameters, Expose Color, Pixel
Image Data for a particular color, and Terminate Exposure) is initiated by the
host computer. the pixel image data is initially downloaded in the dynamic buffer
memory (DRAM) and then subsequently into the video buffer memory (VRAM).
Pixel images are exposed on film with a vertical slow scan where an entire
horizonral line is exposed before the CRT beam is vertically deflected to the next
scan line. Each pixel image is stored in the VRAM’s as a byte value, providing
the ability to distinguish between 256 distinct levels. A typical exposure begins
with the display of all the pixels at the highest level (level 255). After a required
number of scans occurs, the pixels with the next lowest level (level 254) are also
turned on. This process continues until all of the levels, except level 0 which is
always black, have been turned on. Once a pixel is turned on, it is not turned off
until the entire line is exposed.
Upon command from the VRAM control PAL’s, the parallel pixel image data
stored in the VRAM’s is loaded onto shift registers. Refer to paragraph 4 for a
functional description of how the parallel pixel image data is loaded from the
VRAM’s to the shift registers.
The shift registers shift the parallel pixel image data onto four intermediate 8-bit
comparators. The intermediate 8-bit comparators compares the image data from
the VRAM’s with the current exposure level. If the VRAM output is equal to or
greater than the current exposure level, the output of the comparator is a one
value. This comparator output becomes the video signal for the CRT.