Repair manual
2-38
THEORY OF OPERATION
Table 2-9. TIMTBL Control Bits (Con't)
Control Bits Function
VRSR2 VRSR1
1 0 This control function indicates a VRAM intermediate load
2. The row loaded is determined by the upper 6-bits of the
previous DMA1 VRAM load. Row address 1 is a 1 and
row address 0 is a zero.
1 1 This control function indicates a VRAM intermediate load
3. The row loaded is determined by the upper 6-bits of the
previous DMA1 VRAM load. Row address 1 and row
address 0 are one.
f. VRAM Trigger Signal Generation
The VRAM Trigger Signal (VRTRG) is generated by the Horizontal
Signal Generation circuit. For a functional description of the Horizontal
Signal Generation circuit refer to paragraph 7 in thi Section of the Service
Manual.
The VRTRG signal serves a dual purpose. It is used for a read and a shift
register load cycle.
For a read cycle, this signal is used as an output enable signal. If VRTRG
is asserted after the assertion of RAS, then the cycle is a VRAM read
cycle.
If the VRTRG signal is asserted before the assertion of RAS, the cycle is a
VRAM shift register load cycle. In this case, the data lines to the micro
processor are not enabled. Instead, the data that is in the row which is
specified by the row address is loaded into the integral 256x4 bit shift
register. the column address during a shift register load cycle indicates the
first pixel in the row which is shifted out. In all cases, the column address
is zero. The first pixel which is clocked out of the shift register is always
the first pixel in the specified row.
The VRTRG signal is generated by the VROE and the TRGSYNC signals.
A control PAL in the Horizontal Generation circuit generates the VROE