Repair manual

2-37
THEORY OF OPERATION
latched and remembered, then the subsequent intermediate VRAM
shift register load will read the next row in VRAM by using the
upper 7-bits from the most recent DMA controller channel 1 cycle
and setting the LS row address bit to one.
In order to synchronize an intermediate shift register load, a
normal VRAM shift register load cycle must begin before the
current shift register contents are transferred. The beginning of the
cycle does not have to be synchronized with the video clock.
However, the termination of the cycle must occur when the last
pixel from the previous block is clocked out by the serial clock
(SC). The VRAM intermediate shift register load is a TIMTBL
DMA cycle which is extended. It does not terminate until the last
pixel in the current block is clocked out of the VRAM shift
register. A pixel clock is clocked by the serial clock (SC) and
provides a 256 count. This counter expires at the same time that
the VRAM shift register is emptied. When this counter expires, a
TIMTBL DMA cycle which includes an intermediate shift register
load is terminated.
To accomodate up to 2K wide images, the Digital Palette must be
able to generate three intermediate shift registerloads. Also, the
least significant bits of the row address must be manipulated to
specify the applicable VRAM row address.
Two TIMTBL control bits (VRSR1 and VRSR2) determine
whether a TIMTBL DMA will include an intermediate shift
register load and which row will be loaded. Table 2-9 defines the
TIMTBL control bits.
Table 2-9. TIMTBL Control Bits
Control Bits Function
VRSR2 VRSR1
0 0 This contol bit function indicates no intermediate shift
register load. The VRAM,s during this cycle will simply
be refreshed with a CAS before a RAS refresh.
0 1 This control function indicates a VRAM intermediate load
1. The row loaded is determined by the upper 7-bits of the
previous DMA1 VRAM load. Row address bit 0 is a one.