Repair manual
2-36
THEORY OF OPERATION
When the DMA controller counter counts down to zero indicating
that the specified number of horizontal scan lines has occurred and
that the particular level has been exposed, an interrupt service
routine (DMA1ISR) is generated. This interrupt service routine
resets the DMA source address and the DMA counter for the next
VRAM shift register load cycle.
2) Shift Register Load Process
The Digital Palette basic configuration is capable of exposing
images at horizontal resolutions of 512 pixels to 2048 (2K)
pixels. This configuration uses four 4-bit VRAM’s. The VRAM’s
are organized so that two 8-bit pixels are shifted out of their
internal registers simultaneously. Internally, the VRAM’s are
organized as 256 rows; each containing 256, 4-bit values. The
DMA controller channel 1 of the microprocessor, indicated in
paragraph 1, loads the contents of a specific row into the VRAM’s
internal shift register, thus providing 512 bytes of pixel data that is
available for the video image stream.
For horizontal resolutions greater than 512 pixels, a mechanism is
used to reload the VRAM shift registers with the subsequent 512
pixel blocks. It occurs in the middle of a video scan and
in sync with the video clock.
For example, when exposing a 1024 pixel wide image, the DMA
controller channel 1 loads the VRAM shift registers with the first
512 pixels before the shift register clock (SC) starts. This load
occurs while there is no video image being displayed. It can occur
synchrously with the microprocessor clock with no regard to the
video clock. The second 512 pixels must be loaded into the
VRAM shift registers at the same time that the last pixel of the
first block is being shifted out. The second block of 512 pixels
must be from a different row than the first, therefore requiring a
different VRAM address. The row address requirement is satisfied
by specifying in the software that, for a 1K image, all image
buffers in the VRAM must begin on an even 1K boundary in the
VRAM. This guarantees that the least significant (LS) row
address bit is zero. If the DMA controller channel 1 row address is