Repair manual

2-35
THEORY OF OPERATION
DMA controller channel 1 of the microprocessor performs the
VRAM shift register load operation after each horizontal scan line.
It is setup to read a memory location and to write an I/O location.
The internal counter of the DMA controller channel 1 is setup to
decrement after each horizontal scan line and to generate an
interrupt when its count reaches zero.
When the DMA controller channel 1 performs an I/O write cycle
to a particular I/O address it generates a VRAM shift register cycle
signal (VRSRLD) on the select line of the comparator
latch. The cycle signal loads the VRAM shift registers with the
contents of a specific row from the VRAM’s internal shift
registers. The row of data that is selected is specified by the
address lines (LA1 - LA8), providing the ability to load one of 256
different lines. During this I/O write cycle, the low 8-bits of the
data bus are loaded into the comparator latch. This value indicates
the current pixel level. Also, the upper 8-bits of the data bus are
loaded into the luminant latch. The value loaded onto the luminant
latch controls the 8-bit Digital/Analog device in the luminant
circuit. Refer to paragraph 7 for a functional description of the
Luminant circuit.
The Exposure command from the host computer contains the
necessary code information to select a specified table that contains
an entry for each level to be exposed. Each entry in the selected
table contains two pieces of information: data which is sent to the
hardware (pixel and luminace level), and the number of horizontal
scan lines for the particular level.
To expose a horizontal scan line, the DMA controller source
address is set for the particular data in the selected table and the
DMA controller transfer count is set for the number of horizontal
scan lines for specified level. Also, the DMA controller destina-
tion address is set for the VRAM row which contains the
image data for the current horizontal scan line. DMA transfers
are allowed to occur for the current horizontal scan line. A single
DMA controller transfer occurs at the end of each horizontal scan
line.