Repair manual

2-34
THEORY OF OPERATION
Before the timing table is set, or when entries in the timing table are
changed, the TIMTBL DMA should be disabled. This is performed with
a single I/O instruction which asserts the /RFSHEN function for the
RCTLP3 control PAL.
When /RFSHEN is asserted, two things occur: first, HOLD is not
generated by horizontal timing (HTIMP3) PAL and, therefore, TIMTBL
DMA cycles do not occur; second, the signal /RFSHALL is generated
and sent to the RCTLP1 control PAL. /RFSHALL is a gated version of
the refresh enable (/RFSHEN) function which is gated by the /RD signal.
When /RFSHALL is asserted for RCTLP1 control PAL, the CAS before
RAS refresh cycle is performed on the DRAM’s and VRAM’s if the
current cycle is not a read/write cycle to one of the DRAM’s. Therefore,
when /RFSHEN is asserted, the DRAM’s will be refreshed on any
EPROM or I/O read cycle.
e. Loading VRAM Shift Registers
1) DMA Controller Channel 1 Operation
After the video image data is displayed for the horizontal scan line,
the VRAM shift registers are loaded with the VRAM image data
for the subsequent horizontal scan line. This action continues until
all the image data for a particular sequential exposure is
completed. For each horizontal scan line, the current comparator
(pixel) level and the luminant value is also transfered.