Repair manual

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THEORY OF OPERATION
d. DRAM and VRAM Refresh
All of the DRAM’s and VRAM’ have the CAS before the RAS refresh
feature. With this type of feature, row address data is not required to
properly refresh the DRAM’s. For normal operation, the refresh occurs
as part of a TIMTBL DMA cycle.
For DRAM’s, an entry is read from the timing table and then placed
on the Address/Data communications bus. The CAS and output enables
signals for the DRAM and VRAM memories are maintained which
maintains the data. The RAS signal, however, is de-asserted for more
than 100 nsecs and then re-asserted; thus providing a hidden refresh
cycle.
A CAS before RAS refresh cycle is generated for the VRAM’s for all
TIMTBL DMA cycles which do not include an intermediate shift regis
ter load. This refresh cycle occurs while the timing table data is being
read from the DRAM. On average, a DRAM refresh must be generated
every 15 usec. The horizontal scan at 14.7 KHz takes approximately 63
usecs. This means that the timing table must contain at least five entries,
excluding the entries which generate an intermediate shift register load
to the VRAM, to provide the required number of refresh cycles.