Repair manual

2-32
THEORY OF OPERATION
Table 2-8. RAM Control PAL’s
Control PAL Function
RCTLP1 The RCTLP1 control PAL provides the following operation signals:
o RSEL2 - Control signals sent to the RAM Address Multiplexer
RSEL1 PALS, RCTLP4 and RCTLP5. These control lines
RSELO are used to indicate which addresses are sent to the
DRAMS and VRAMS.
o VCASEN - VRAM CAS enable. Asserted when CAS (Column
Address Strobe) should be asserted on the VRAMS.
o DCASEN - DRAM CAS enable. Asserted when CAS should be
asserted to the DRAMs.
o DRAS - This is the RAS (Row Address Strobe) signal for the
DRAM devices.
o VRAS - This is the RAS signal for the VRAM devices.
RCTLP2 This RAM control PAL generates the necessary memory CAS signals. It
also generates the write enable signal (/VRWE) and the output enable
signal (/VROE) for the VRAM’s.
RCTLP3 This RAM control PAL generates all the signals that control the
miscellaneous memory functions. The functions are:
o /RFSHEN - This function is the refresh enable. It is set or reset
by a single I/O instruction. When it is asserted, the
TIMTBL DMA transactions occur. When enable is
not true, refresh cycles occurs on every read cycle
which does not involve the DRAM or VRAM.
o /DROE - This function is the DRAM ouput enable.
o /DRWE - This function is the DRAM write enable.
o RA8 - This function is the ninth address line for the 512K
DRAM configuration. It multiplexes address lines
LA 17 and LA 18.
o Internal - This function is used to implement a
Registers 4-bit counter which provides the offset into the
timing table during a TIMTBL DMA transaction.
RCTLP4/5 These RAM control PAL’s serve as address multiplexers. They generate
the RAM address signal (RA0 - RA7). They are implemented with 14
input lines and 4 output lines.