Repair manual

2-31
THEORY OF OPERATION
The Digital Palette with the optional VRAM’s added (Additional 128K
of VRAM) provides the ability to expose images with a horizontal
resoultion up to 4096 pixels.
Refer to paragraph d for a functional explanation of the VRAM Internal
Shift Register.
c. RAM Control PAL’s (Figure 2-9, sheet 3)
There are two types of memory transactions (transfers) for the DRAM
and VRAM memory: when the microprocessor controls the Address/Data
communications bus and when the DMA Channel Controller HOLD/
HLDA (TIMTBL) cycle of the microprocessor controls the Address/Data
communications bus.
When the microprocessor controls the Address/Data communications bus,
the following memory transactions take place:
o DRAM (128K) Read/Write Cycle
o DRAM (512K) Read/Write Cycle
o VRAM (2K Mode) Video Resolution Read/Write Cycle
o VRAM (4K Mode) Video Resolution Read/Write Cycle
When the DMA Channel Controller Hold/HLDA (TIMTBL) cycle of the
microprocessor controls the Address/Data communications bus, the
following memory transactions take place:
o DRAM (128K) reads DMA Channel Controller Hold/HLDA
(TIMTBL) entry (no intermediate VRAM shift register load
occurs)
o VRAM intermediate shift register load 1 (VRSRINTLD1)
o VRAM intermediate shift register load 2 (VRSRINTLD2)
o VRAM intermediate shift register load 3 (VRSRINTLD3)
Both types of memory transactions are controlled by five RAM control
PAL’s (Figure 2-9, sheet 3). Table 2-8 lists and defines the function each
of the RAM Control PAL’s.