Repair manual

2-28
THEORY OF OPERATION
Table 2-7. Microprocessor Control PAL Select Signals
Select Signal Function
SCSICS Asserted during an IO read/write cycle to the optional
SCSI device. This signal is guaranteed to be asserted only
while the address lines are stable.
DRAMCS Asserted during a memory read/write cycle to the base
128K bytes of memory.
VRAMCS Asserted druing a memory read/write cycle to the
VRAMS.
NOTE: For memory read/write cycles to the optional 512K
DRAM, both DRAMCS and VRAMCS are as-
serted. Both of these signals go to the RAM
control PAL, RCTLP1, which generates the appro-
priate control signals to the memory devices.
VRSALD VRAM Shift Register Load. This signal is asserted on any
IO read/write cycle to the IO addresses 800hex to FFEhex.
(LA11 is high) during this cycle, the VRAMS will load a
row of data into their internal shift registers.
XRAMCS This signal is asserted on any memory read/write cycle
to access additional memory on an expansion board. This
expansion option does not currently exist.
TRANSEN This signal controls the data buffers for the optional SCSI
board.
LALECLR This signal clears the latch which generates LALE.
LALE is asserted on the rising edge of OUTCLK and must
be deasserted on the falling edge of OUTCLK to guarantee
that the address lines are valid for the entire duration of
LALE