Repair manual

2-27
THEORY OF OPERATION
For detailed information pertaining to the RESET command from
the host computer, refer to the Digital Palette Product
Specification Manual or the applicable Parallel Port Interface
Specifications Manual.
d. Address Latches
Address latches (figure 2-9, sheet 1) are used because the microprocessor
has a multiplexed address/data communications bus. At the beginning of
a memory or an I/O cycle, the applicable address appears on the
communications bus. It must be externally latched by the address latch.
Data will appear on the communications bus during the remainder of the
memory or I/O cycle.
e. Microprocessor Control PAL
The Microprocessor Control PAL (Figure 2-9, sheet 1) provide the
necessary decoded select signals for the Digital Palette Buffer Memory
(DRAM and VRAM Memory). It also provides select signals for the
optional SCSI interface.
Specified select signals from the microprocessor Control PAL download
the image data initially stored in the DRAM memory into VRAM
memory. From VRAM memory, the image data is sent to the Video
Generation circuit where it is processed into a serial VIDEO signal that
turns on the CRT in the Monitor P.C. Board.
Table 2-7, on the following page, lists and describes the function of each
of the decoded select signals.