Repair manual

2-24
THEORY OF OPERATION
Table 2-6. Clock Signals from Microprocessor
Clock Signal Function
OUTCLK This microprocessor clock signal operates:
o Control PAL for the microprocessor.
o Addressable latches for the microprocessor.
o Control PAL’s for the Horizontal Timing Generator.
o Addressable latch for the optional SCSI Parallel
Interface.
HSYNC This microprocessor clock signal operates:
o Horizontal Sync Driver. (This Horizontal Sync Driver
produces the necessary Horizontal Sync signal
(MONHS) that operates the Horizontal Deflection
network on the Monitor P.C. Board.
o Horizontal Timing Generator.
o Horizontal Frequency Synthesizer.
XTALHS This microprocessor clock signal, in conjunction with the
HSYNC clock signal, operates the Horizontal Frequency
Synthesizer.
c. Reset Control
The Reset Control circuit (Figure 2-9, sheet 1) provides a reset signal that
initializes the Microprocessor Control network and its associated
circuitry. This reset signal is generated automatically when the computer
Imager is first powered up (turned on) or when the user momentarily
presses the RESET switch on the rear panel of the Digital Palette.
1) Power Up Reset
When the Digital Palette is turned on, the RC network in the
Reset Control circuit generates a power reset signal that is applied
to the reset line of the microprocessor. This signal initializes the
microprocessor. The microprocessor generates a RESET and a
clear signal that initializes its associated circuitry.