Repair manual

2-23
THEORY OF OPERATION
5) Programmable Memory
The Microprocessor Control Network (Figure 2-9, sheet 1) uses
three types of memory:
o Erasable Programmable Read Only (EPROM)
o Dynamic Random Access Memory (DRAM)
o Video Random Access Memory VRAM)
Refer to the paragraphs D3, D4, and D5 for a detailed description
of how the Microprocessor Control Network uses its available
memory.
b. 40 MHz Clock
The 40 MHz Clock is a crystal oscillator (Figure 2-9, sheet 1) that
provides the necessary clock pulses to run the Microprocessor and its
associated circuitry.
When the Digital Palette is powered up, the crystal oscillator generates
a 40 MHz clock (UP CLK) signal. This UP CLK signal provides the
necessary clock pulses that operate the microprocessor. It also provides
the necessary clock pulses that operate the RAM Timing Control PAL
(RCTLP1) in the RAM Contol circuit. Refer to the paragraph 3 for a
functional description of RAM Timing Control PAL.
The UP CLK signal is reduced to 20 Mhz clock signal by the divide-by-2
network and then applied to the clock input of the microprocessor. This
inputted clock signal provides the necessary internal timing for the
microprocessor.
The microprocessor, in turn, divides its input clock signal by 1/2 and then
outputs three clock signals to the associated circuits that are required to
operate synchronously with it. Table 2-6 lists and defines the clock
signals outputted by the microprocessor.