Repair manual

2-22
THEORY OF OPERATION
4) DMA Controller Channels
The microprocessor has two general purpose DMA controller
channels: DMA controller channel 0 and DMA controller channel
1. It also has a third type DMA controller channel transfer that is
generated externally. Table 2-5 lists and describes the DMA
controller channels.
Table 2-5. DMA Controller Channels
DMA Controller Channel Function
DMA 0 This DMA controller channel is available for
general tasks. It is available for DMA transactions
from the optional SCSI port.
DMA 1 This DMA controller channel is dedicated to
performing a VRAM shift register load at the end
of the active video time of the horizontal scan. It
will read a word from a table in memory and write
to VRAM.
This special write will consider the address as the
VRAM row which is loaded into VRAM shift
register. This data which is written during this
transfer contains the comparator value and the
luminant level. The comparator value is in the low
byte and the luminant level is in the high byte.
DMA External This external DMA controller channel is used to
update the horizontal time. It is also used to
provide refresh cycles to the DRAM and VRAM
memory. This refresh cycle is called the TIMTBL
DMA cycle. It uses the HOLD/HLDA signals from
the microprocessor.