Repair manual

2-20
THEORY OF OPERATION
3) Device I/O Select Lines
The microprocessor has 64 Kbytes of I/O space. Within this I/O
space, the microprocessor is capable of generating select signals
for up to seven devices. The select lines are active for seven
contiguous blocks of 128 bytes above a programmable base
address. This base address is set by the start up code to be 0x0000
in the I/O space.
Table 2-4 lists and describes the microprocessor’s select lines that
control the various devices on the Logic Controller P.C. Board.
Table 2-4. Device I/O Select Lines
Select Line Function
PCSO This select line is asserted for I/O addresses 0x0000 to
0x7F. Address Bit 1 is the only address line in this space
which is important.
When this bit is low, DMA controller channel 0 and 1
transactions are disabled. When high, DMA controller
channel 0 and 1 transactions are enabled.
Therefore, a write to I/O address 0 disables DMA
tranactions and a write to I/O address 2 enables I/O
transactions. During these write cycles, the content select
lines are ignored. This capability is required in interrupt
service routines which are time critical. It is important in
these routines to disable further innterrupts and guarantee
that DMA transactions will not occur. In these routines,
the DMA controller channels are temporarily disabled
until the time critical portion of the routine has run.
PCS1 This select line is asserted for I/O addresses 0x80 to 0xFF.
Its I/O space is dedicated to the Centronics Port. Address
Bit 1 is the only address line in this space which is
important.
The I/O map for this space is:
0x0080 WR - Centronics Data Port Write
0x0080 RD - Centronics Data and Control Port
0x0082 WR - Centronics Control Port Write