Owner`s manual

Figure 4–41: Timer Interrupt Vector Register (TIVR0)
3
1 109 210
MUST BE ZERO
SCB Vector Offset
msb−p334−90
MBZ
Figure 4–42: Timer Control Register 1 (TCR1)
3
1
3
0 87654 2 0
MUST BE ZERO 0 0
Error (ERR) Interrupt (INT)
msb−p331−90
Interrupt Enable (IE)
Single (SGL)
Transfer (XFR)
Stop (STP)
Run (RUN)
Figure 4–43: Timer Interval Register (TIR1)
3
1 0
Timer Interval Register
msb−p332−90
KA65A CPU Module Registers 4–25