Owner`s manual

5–18 EEPROM Control Register (EECTL) ................... 5–10
5–19 Timeout Control/Status Register (TMOER) . ............. 5–10
6–1 Device Register (XDEV) ............................. 6–3
6–2 Bus Error Register (XBER) .......................... 6–4
6–3 Failing Address Register (XFADR) ..................... 6–5
6–4 Responder Error Address Register (AREAR) ............. 6–5
6–5 DWMBB/A Error Summary Register (AESR) ............. 6–6
6–6 Interrupt Mask Register (AIMR) ...................... 6–7
6–7 Implied Vector Interrupt Destination/Diagnostic Register
(AIVINTR) . ...................................... 6–7
6–8 Diag 1 Register (ADG1) ............................. 6–8
6–9 Utility Register (AUTLR) ............................ 6–8
6–10 Control and Status Register (ACSR) ................... 6–9
6–11 Return Vector Register (ARVR) . ...................... 6–9
6–12 Failing Address Extension Register (XFAER) ............ 6–10
6–13 BI Error Address Register (ABEAR) ................... 6–10
6–14 Control and Status Register (BCSR) ................... 6–11
6–15 DWMBB/B Error Summary Register (BESR) ............. 6–11
6–16 Interrupt Destination Register (BIDR).................. 6–12
6–17 Timeout Address Register (BTIM) ..................... 6–12
6–18 Vector Offset Register (BVOR) . . ...................... 6–12
6–19 Vector Register (BVR) .............................. 6–13
6–20 Diagnostic Control Register 1 (BDCR1) ................. 6–13
6–21 Page Map Register (PMR) ........................... 6–13
6–22 VAXBI Device Register (DTYPE) ...................... 6–14
7–1 Vector Length (VLR) and Vector Count (VCR) Registers .... 7–2
7–2 Vector Mask Register (VMR) . . . ...................... 7–2
7–3 Vector Interface Error Status Register (VINTSR) ......... 7–7
7–4 Accelerator Control and Status Register (ACCS) .......... 7–7
7–5 Vector Processor Status Register (VPSR) . . . ............. 7–8
7–6 Vector Arithmetic Exception Register (VAER) ............ 7–8
7–7 Vector Memory Activity Check Register (VMAC) .......... 7–9
7–8 Vector Translation Buffer Invalidate All Register (VTBIA) . . 7–9
7–9 Vector Indirect Address Register (VIADR) . . ............. 7–9
7–10 Vector Indirect Data Low Register (VIDLO) . ............. 7–10
7–11 Vector Indirect Data High Register (VIDHI) ............. 7–10
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