Owner`s manual

Figure 4–4: Console Transmitter Control and Status Register (TXCS)
3
1 8765 3210
MUST BE ZERO MBZ
Transmitter Ready (TX RDY)
Transmitter Interrupt Enable (TX IE)
Loopback
Transmit Break (XMIT BRK)
0
msb−p268−90
Figure 4–5: Console Transmitter Data Buffer Register (TXDB)
3
1870
MUST BE ZERO
Transmit Data
msb−p269−90
Figure 4–6: Machine Check Error Summary Register (MCESR)
3
1 0
Machine Check Error Summary Register (MCESR)
msb−p270−90
KA65A CPU Module Registers 4–9