Owner`s manual

Table 4–2 (Cont.): KA65A Internal Processor Registers
Address
decimal (hex) Register Mnemonic Type
1
Class
2
126 (7E) Primary Cache Error Address PCERR R/W 2
127 (7F) Primary Cache Status PCSTS R/W 2 Init
128–143 (80–8F) Reserved 3
144 (90) Vector Processor Status VPSR R/W 2
145 (91) Vector Arithmetic Exception VAER RO 6
146 (92) Vector Memory Activity Check VMAC RO 6
147 (93) Vector Translation Buffer In-
validate All
VTBIA WO 6
148–156 (94–9C) Reserved 5
157 (9D) Vector Indirect Register Ad-
dress
VIADR R/W 6
158 (9E) Vector Indirect Data Low VIDLO R/W 6
159 (9F) Vector Indirect Data High VIDHI R/W 6
160–255 (A0–FF) Reserved 3
256 (100) and
up
Reserved 4
1
See Table 4–1.
2
Key to Classes:
1 = Implemented by the KA65A CPU module as specified in the VAX Architecture Refer-
ence Manual.
2 = Implemented uniquely by the KA65A CPU module.
3 = Not implemented. Read as zero; NOP on write. These registers should not be refer-
enced during normal operation as no other instructions can be executed by the CPU un-
til a timeout period that might be longer than device or CPU timeouts has ex-
pired.
4 = Access not allowed; accesses result in a reserved operand fault.
5 = Accessible, but not fully implemented; accesses yield UNPREDICTABLE re-
sults.
6 = Implemented by the FV64 vector module.
n Init = The register is initialized on a KA65A CPU module reset (power-up, system re-
set, and node reset).
KA65A CPU Module Registers 4–7