Owner`s manual

Table 4–2 (Cont.): KA65A Internal Processor Registers
Address
decimal (hex) Register Mnemonic Type
1
Class
2
58 (3A) Translation Buffer Invalidate
Single
TBIS WO 1
59 (3B) Translation Buffer Data TBDATA WO 2
60–61 (3C–3D) Reserved 3
62 (3E) System Identification SID RO 1
63 (3F) Translation Buffer Check TBCHK WO 1
64–111 (40#–#6F) Reserved 3
112 (70) Backup Cache Index BCIDX R/W 2
113 (71) Backup Cache Status BCSTS R/W 2 Init
114 (72) Backup Cache Control BCCTL R/W 2 Init
115 (73) Backup Cache Error Address BCERA RO 2
116 (74) Backup Cache Tag Store BCBTS R/W 2
117 (75) Backup Cache Deallocate Tag BCDET WO 2
118 (76) Backup Cache Error Tag BCERT RO 2
119–122 (77–7A) Backup Cache Reserved BC119–BC122 R/W 5
123 (7B) Vector Interface Error Sta-
tus
VINTSR R/W 2
124 (7C) Primary Cache Tag Array PCTAG R/W 2
125 (7D) Primary Cache Index PCIDX R/W 2
1
See Table 4–1.
2
Key to Classes:
1 = Implemented by the KA65A CPU module as specified in the VAX Architecture Refer-
ence Manual.
2 = Implemented uniquely by the KA65A CPU module.
3 = Not implemented. Read as zero; NOP on write. These registers should not be refer-
enced during normal operation as no other instructions can be executed by the CPU un-
til a timeout period that might be longer than device or CPU timeouts has ex-
pired.
4 = Access not allowed; accesses result in a reserved operand fault.
5 = Accessible, but not fully implemented; accesses yield UNPREDICTABLE re-
sults.
6 = Implemented by the FV64 vector module.
n Init = The register is initialized on a KA65A CPU module reset (power-up, system re-
set, and node reset).
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