Owner`s manual

Table 4–2 (Cont.): KA65A Internal Processor Registers

Address

decimal (hex) Register Mnemonic Type

Class

34 (22) Console Transmitter Control/

Status

TXCS R/W 2 Init

35 (23) Console Transmitter Data Buffer TXDB WO 2 Init

36–37 (24–25) Reserved 3

38 (26) Machine Check Error Sum-

mary

MCESR WO 2

39 (27) Reserved 3

40 (28) Accelerator Control and Sta-

tus

ACCS R/W 2 Init

41 (29) Reserved 3

42 (2A) ConsoleSaved Program Counter SAVPC RO 2

43 (2B) Console Saved Processor Sta-

tus Longword

SAVPSL RO 2

44–46 (2C–2E) Reserved 3

47 (2F) Translation Buffer Tag TBTAG WO 2

48–54 (30–36) Reserved 3

55 (37) I/O Reset IORESET WO 2

56 (38) Memory Management Enable MAPEN R/W 1 Init

57 (39) Translation Buffer Invalidate

All

TBIA WO 1

See Table 4–1.

Key to Classes:

1 = Implemented by the KA65A CPU module as speciﬁed in the VAX Architecture Refer-

ence Manual.

2 = Implemented uniquely by the KA65A CPU module.

3 = Not implemented. Read as zero; NOP on write. These registers should not be refer-

enced during normal operation as no other instructions can be executed by the CPU un-

til a timeout period that might be longer than device or CPU timeouts has ex-

pired.

4 = Access not allowed; accesses result in a reserved operand fault.

5 = Accessible, but not fully implemented; accesses yield UNPREDICTABLE re-

sults.

6 = Implemented by the FV64 vector module.

n Init = The register is initialized on a KA65A CPU module reset (power-up, system re-

set, and node reset).

KA65A CPU Module Registers 4–5