Owner`s manual

Table 4–2 (Cont.): KA65A Internal Processor Registers
Address
decimal (hex) Register Mnemonic Type
1
Class
2
18 (12) Interrupt Priority Level IPL R/W 1 Init
19 (13) AST Level ASTLVL R/W 1 Init
20 (14) Software Interrupt Request SIRR WO 1
21 (15) Software Interrupt Summary SISR R/W 1 Init
22–23 (16–17) Reserved 3
24 (18) Interval Clock Control and
Status ICCS
R/W 2 Init
25–26 (19–1A) Reserved 3
27 (1B) Time-of-Year Clock
3
TODR R/W 1
28 (1C) Console Storage Receiver Sta-
tus
CSRS R/W 5 Init
29 (1D) Console Storage Receiver Data CSRD RO 5 Init
30 (1E) Console Storage Transmitter
Status
CSTS R/W 5 Init
31 (1F) Console Storage Transmitter
Data
CSTD WO 5 Init
32 (20) Console ReceiverControl/Status RXCS R/W 2 Init
33 (21) Console Receiver Data Buffer RXDB RO 2 Init
1
See Table 4–1.
2
Key to Classes:
1 = Implemented by the KA65A CPU module as specified in the VAX Architecture Refer-
ence Manual.
2 = Implemented uniquely by the KA65A CPU module.
3 = Not implemented. Read as zero; NOP on write. These registers should not be refer-
enced during normal operation as no other instructions can be executed by the CPU un-
til a timeout period that might be longer than device or CPU timeouts has ex-
pired.
4 = Access not allowed; accesses result in a reserved operand fault.
5 = Accessible, but not fully implemented; accesses yield UNPREDICTABLE re-
sults.
6 = Implemented by the FV64 vector module.
n Init = The register is initialized on a KA65A CPU module reset (power-up, system re-
set, and node reset).
3
TODR is maintained during power failure by the XMI TOY BBU PWR line on the XMI back-
plane.
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