Owner`s manual

4–51 Failing DAL Register 3 (FDAL3) ...................... 4–28
4–52 Interprocessor Implied Vector Interrupt Generation Register
(IPIVINTR) ...................................... 4–28
4–53 Write Error Implied Vector Interrupt Generation Register
(WEIVINTR) ..................................... 4–29
4–54 Device Register (XDEV) ............................. 4–30
4–55 Bus Error Register 0 (XBER0) . . ...................... 4–31
4–56 Failing Address Register (XFADR0) .................... 4–32
4–57 XMI General Purpose Register (XGPR) ................. 4–32
4–58 Node Specific Control and Status Register (NSCSR0) . ..... 4–32
4–59 XMI Control Register 0 (XCR0) . ...................... 4–33
4–60 Failing Address Extension Register 0 (XFAER0) .......... 4–33
4–61 Bus Error Extension Register 0 (XBEER0) . ............. 4–34
4–62 Writeback 0 Failing Address Register (WFADR0) ......... 4–35
4–63 Writeback 1 Failing Address Register (WFADR1) ......... 4–35
4–64 Machine Check Stack Frame . . . ...................... 4–36
4–65 KA65A Machine Check Parse Tree..................... 4–41
4–66 KA65A Hard Error Interrupt Parse Tree . . . ............. 4–46
4–67 KA65A Soft Error Interrupt Parse Tree ................. 4–49
5–1 Device Register (XDEV) ............................. 5–2
5–2 Bus Error Register (XBER) .......................... 5–2
5–3 Starting and Ending Address Register (SEADR) .......... 5–3
5–4 Memory Control Register 1 (MCTL1) ................... 5–3
5–5 Memory ECC Error Register (MECER) ................. 5–4
5–6 Memory ECC Error Address Register (MECEA) .......... 5–4
5–7 Memory Control Register 2 (MCTL2) ................... 5–5
5–8 TCY Tester Register (TCY)........................... 5–5
5–9 Block State ECC Error Register (BECER) . . ............. 5–6
5–10 Block State ECC Address Register (BECEA) ............. 5–6
5–11 Starting Address Register (STADR) .................... 5–7
5–12 Ending Address Register (ENADR) .................... 5–7
5–13 Segment/Interleave Register (INTLV) .................. 5–7
5–14 Memory Control Register 3 (MCTL3) ................... 5–8
5–15 Memory Control Register 4 (MCTL4) ................... 5–8
5–16 Block State Control Register (BSCTL) .................. 5–9
5–17 Block State Address Register (BSADR) ................. 5–9
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