Owner`s manual

VCTL_DOP_LOW register, 7–16
VCTL_ILL register, 7–18
VCTL_LDST register, 7–17
VCTL_STRIDE register, 7–17
Vector Arithmetic Exception
Register, 7–8
Vector Controller Status Register,
7–19
Vector Count Register, 7–1
Vector Indirect Address Register,
7–9
Vector Indirect Data High Register,
7–10
Vector Indirect Data Low Register,
7–10
Vector indirect registers, 7–11 to
7–27
Vector Interface Error Status
Register, 4–15, 7–7
Vector Length Register, 7–1
Vector Mask High Register, 7–13,
7–24
Vector Mask Low Register, 7–12,
7–24
Vector Mask Register, 7–1
Vector Memory Activity Register,
7–9
Vector Offset Register, 6–12
Vector Processor Status Register,
7–8
Vector Register, 6–13
Vector Register n, 7–11
Vector Translation Buffer Invalidate
All Register, 7–9
/VE qualifier, 7–1
VIADR register, 7–9
VIDHI register, 7–10
VIDLO register, 7–10
VINTSR, 4–15
VINTSR register, 7–7
VLR, 7–1
VMAC register, 7–9
VMR, 7–1
VPSR register, 7–8
VREGn register, 7–11
VTBIA register, 7–9
W
WEIVINTR, 4–29
WFADR0, 4–35
WFADR1, 4–35
Writeback 0 Failing Address
Register, 4–35
Writeback 1 Failing Address
Register, 4–35
Write Error Implied Vector Interrupt
Generation Register, 4–29
X
XBEER0, 4–34
XBER, 5–2, 6–4
XBER0, 4–31
XCR0, 4–33
XDEV, 4–30, 5–2, 6–3
XFADR, 6–5
XFADR0, 4–32
XFAER, 6–10
XFAER0, 4–33
XGPR, 4–32
XMI address space, 3–5
XMI Control Register 0, 4–33
XMI General Purpose Register, 4–32
XMI I/O space address allocation,
3–3
XMI memory and I/O address space,
3–2
XMI required registers, 6–3
XMI slot numbers, 3–1
XMI-to-VAXBI adapter
self-test results, 2–5
Index–6