Owner`s manual

Self-test (Cont.)
sample, 2–1 to 2–5
VAXBI module test results, 2–5
when invoked, 2–1
SID, 4–12
Soft error interrupt parse tree
FV64A, 7–30
KA65A, 4–49 to 4–50
SSCBAR, 4–20
SSCBTR, 4–21
SSCCNR, 4–21
SSICR, 4–26
STADR, 5–7
Starting Address Register, 5–7
Starting and Ending Address
Register, 5–3
System Base Register, 7–21
System Identification Register, 4–12
System Length Register, 7–22
T
TBDATA, 4–11
TBTAG, 4–11
TCR0, 4–24
TCR1, 4–25
TCY, 5–5
TCY Tester Register, 5–5
Timeout Address Register, 6–12
Time-Out Control/Status Register,
5–10
Timer Control Register, 4–24
Timer Control Register 1, 4–25
Timer Interrupt Vector Register,
4–25
Timer Interrupt Vector Register 1,
4–26
Timer Interval Register, 4–25
Timer Interval Register 0, 4–24
Timer Next Interval Register, 4–24,
4–26
TIR0, 4–24
TIR1, 4–25
TIVR0, 4–25
TIVR1, 4–26
TMOER, 5–10
TNIR0, 4–24
TNIR1, 4–26
Translation Buffer Control Register,
7–22
Translation Buffer Data Register,
4–11
Translation Buffer Invalidate All
Register, 7–23
Translation Buffer Invalidate Single
Register, 7–23
Translation Buffer PTE Register,
7–27
Translation Buffer Tag Register,
4–11, 7–26
Trap2 bit, 4–37
TXCS, 4–9
TXDB, 4–9
U
Unlock Write Pending (UWP) bit,
4–37
Utility Register, 6–8
UWP (Unlock Write Pending) bit,
4–37
V
VAER register, 7–8
VAXBI adapters
self-test, 2–5
VAXBI address space, 3–6 to 3–7
VAXBI Device Register, 6–14
VAXBI modules
self-test, 2–5
VAXBI nodespace and window space
address assignments, 3–7
VAXBI registers, 3–8
VCR, 7–1
VCTL_CALU register, 7–14
VCTL_COP_HI register, 7–15
VCTL_COP_LOW register, 7–15
VCTL_CSR register, 7–19
VCTL_DALU register, 7–15
VCTL_DOP_HI register, 7–16
Index–5