Owner`s manual

MCTL3, 5–8
MCTL4, 5–8
MECEA, 5–4
MECER, 5–4
Memory Control Register 1, 5–3
Memory Control Register 2, 5–5
Memory Control Register 3, 5–8
Memory Control Register 4, 5–8
Memory ECC Error Address
Register, 5–4
Memory ECC Error Register, 5–4
Memory Management Enable
Register, 7–23
Module Revision Register, 7–20
MOD_REV register, 7–20
/M qualifier, 7–1
MSSC Bus Timeout Control
Register, 4–21
MSSC Configuration Register, 4–21
MSSC Input Port Register, 4–22
MSSC Interval Counter Register,
4–26
MSSC Output Port Register, 4–22
N
Nodespace, 3–4
Node Specific Control and Status
Register, 4–32
NSCSR0, 4–32
O
OPORT, 4–22
P
P0 Base Register, 7–20
P0 Length Register, 7–20
P1 Base Register, 7–21
P1 Length Register, 7–21
Page Map Register, 6–13
Parse trees
FV64A, 7–28 to 7–31
KA65A, 4–41 to 4–50
PCERR, 4–16
PCIDX, 4–16
PCSTS, 4–17
PCTAG, 4–16
PMR, 6–13
Primary Cache Error Address
Register, 4–16
Primary Cache Index Register, 4–16
Primary Cache Status Register,
4–17
Primary Cache Tag Array Register,
4–16
R
R5 bit functions
ULTRIX, 1–10
VMS, 1–10
Registers
DWMBB, 6–2
finding in VAXBI address space,
3–6 to 3–7
finding in XMI address space, 3–5
internal processor, 7–3 to 7–10
VAXBI, 3–8
XMI required, 6–3
Responder Error Address Register,
6–5
Restart button, 1–3
Return Vector Register, 6–9
RSSC Base Address Register, 4–20
RXCS, 4–8
RXDB, 4–8
S
SAVPC, 4–10
SAVPSL, 4–10
Scalar Operand High Register, 7–12
Scalar Operand Low Register, 7–12
SEADR, 5–3
Segment/Interleave Register, 5–7
Self-test
explanation of sample
configuration, 2–3
line
XBI, 2–4 to 2–5
Index–4