Owner`s manual

Failing Address Extension Register
0, 4–33
Failing Address Register, 4–32, 6–5
Failing DAL Register 0, 4–27
Failing DAL Register 1, 4–27
Failing DAL Register 2, 4–28
Failing DAL Register 3, 4–28
FDAL0, 4–27
FDAL1, 4–27
FDAL2, 4–28
FDAL3, 4–28
First Part Done (FPD) bit, 4–37
FPD (First Part Done) bit, 4–37
H
Hard error interrupt parse tree
FV64A, 7–29
KA65A, 4–46 to 4–48
I
I/O Reset Register, 4–11
I/O space, 3–2, 3–3
I-box, 4–40
ICCS, 4–8
Illegal Instruction Register, 7–18
Implied Vector Interrupt
Destination/Diagnostic
Register, 6–7
Internal processor registers, 7–3 to
7–10
Interprocessor Implied Vector
Interrupt Generation Register,
4–28
Interrupt Destination Register, 6–12
Interrupt Mask Register, 6–7
Interval Clock Control and Status
Register, 4–8
INTLV, 5–7
IORESET, 4–11
IPIVINTR, 4–28
IPORT, 4–22
K
KA65A vector registers, 7–7
Key switch
lower, 1–3
upper, 1–3
L
LEDs after self-test, 2–6
Load/Store Exception Register, 7–22
Load/Store Instruction Register,
7–17, 7–25
Load/Store Stride Register, 7–17,
7–24
LSX_CCSR register, 7–26
LSX_EXC register, 7–22
LSX_INST register, 7–25
LSX_MAPEN register, 7–23
LSX_MASKHI register, 7–24
LSX_MASKLO register, 7–24
LSX_P0BR register, 7–20
LSX_P0LR register, 7–20
LSX_P1BR register, 7–21
LSX_P1LR register, 7–21
LSX_PTE register, 7–27
LSX_SBR register, 7–21
LSX_SLR register, 7–22
LSX_STRIDE register, 7–24
LSX_TBCSR register, 7–22
LSX_TBIA register, 7–23
LSX_TBIS register, 7–23
LSX_TBTAG register, 7–26
M
Machine Check Error Summary
Register, 4–9
Machine check exceptions, 4–36
Machine check parse tree
FV64A, 7–28
KA65A, 4–41 to 4–45
MBZ (Must be zero), 4–2
MCESR, 4–9
MCTL1, 5–3
MCTL2, 5–5
Index–3