Owner`s manual

Figure 7–39: Memory Management Enable (LSX_MAPEN)
3
1 0
Memory Management Enable Register (A Pseudo Register)
msb−p135−90
Figure 7–40: Translation Buffer Invalidate All Register (LSX_TBIA)
3
1 0
Translation Buffer Invalidate All
msb−p136−90
Figure 7–41: Translation Buffer Invalidate Single Register (LSX_TBIS)
3
1 0
Translation Buffer Invalidate Single
msb−p137−90
Vector Module Registers 7–23