Owner`s manual

Figure 7–21: Deferred ALU Instruction Register (VCTL_DALU)
3
1
2
4
2
3
2
2
1
6
1
5
1
4
1
3
1
2
1
187430
Opcode
Masked Operations Enable (MOE)
Modify Intent (MI)
Vector Register A (VRA)
Vector Register B (VRB)
Vector Register C (VRC)
msb−p146−90
0 Vector Length 0
Match True/False (MTF)
Exception Enable (EXC) or
Figure 7–22: Current ALU Operand Low Register (VCTL_COP_LOW)
3
1 0
Scalar Operand Low
msb−p147−90
Figure 7–23: Current ALU Operand High Register (VCTL_COP_HI)
3
1 0
Scalar Operand High
msb−p148−90
Vector Module Registers 7–15