Owner`s manual

7.4 FV64A Registers — Vector Indirect Registers
Figure 7–12: Vector Register n (VREG n )
6
3 0
Element 0
:
:
:
.
.
.
:
:
:
msb−p138−90
Element 63
Figure 7–13: Arithmetic Exception Register (ALU_OP)
3
1
2
6
2
5
2
4
2
3
2
0
1
9
1
8
1
7
1
4
1
3 9876543 0
Opcode
Vector Length Bit<6> (VL<6>)
Vector Length Bit<5> (VL<5>)
Function
msb−p139−90
Vector Register A (VRA)
Mask Operate Enable (M)
Vector Length Bit<3> (VL<3>)
Vector Length Bit<2> (VL<2>)
Vector Length Bit<1> (VL<1>)
Vector Length Bit<4> (VL<4>)
Mask Sense (S)
Vector Register B (VRB)
Vector Length Bit<0> (VL<0>)
Vector Register C (VRC)
Vector Module Registers 7–11