Owner`s manual

Figure 7–7: Vector Memory Activity Check Register (VMAC)
3
1 0
Vector Memory Activity Check Register
msb−p124−90
Figure 7–8: Vector Translation Buffer Invalidate All Register (VTBIA)
.
3
1 0
Vector Translation Buffer Invalidate All Register
msb−p125−90
Figure 7–9: Vector Indirect Address Register (VIADR)
3
1
1
1
1
00
MUST BE ZERO
Register Field Address
msb−p126−90
Vector Module Registers 7–9