Owner`s manual

Table 7–2 (Cont.): FV64A Registers—Vector Indirect Registers
Register Mnemonic
Register Field
Address (hex) Type
Current ALU Operand Low VCTL_COP_LO 482 R/W
Current ALU Operand High VCTL_COP_HI 483 R/W
Deferred ALU Operand Low VCTL_DOP_LO 484 R/W
Deferred ALU Operand High VCTL_DOP_HI 485 R/W
Load/Store Instruction VCTL_LDST 486 R/W
Load/Store Stride VCTL_STRIDE 487 R/W
Illegal Instruction VCTL_ILL 488 R/W
Vector Controller Status VCTL_CSR 489 R/W
Module Revision MOD_REV 48A R
Vector Copy—P0 Base LSX_P0BR 500 WO
Vector Copy—P0 Length LSX_P0LR 501 WO
Vector Copy—P1 Base LSX_P1BR 502 WO
Vector Copy—P1 Length LSX_P1LR 503 WO
Vector Copy—System Base LSX_SBR 504 WO
Vector Copy—System Length LSX_SLR 505 R/W
Load/Store Exception LSX_EXC 508 RO
Translation Buffer Control LSX_TBCSR 509 WO
Vector Copy—Memory Man-
agement Enable
LSX_MAPEN 50A WO
Vector Copy—Translation Buffer
Invalidate All
LSX_TBIA 50B WO
Vector Copy—Translation Buffer
Invalidate Single
LSX_TBIS 50C WO
Vector Mask Low LSX_MASKLO 510 WO
Vector Mask High LSX_MASKHI 511 WO
Load/Store Stride LSX_STRIDE 512 WO
Load/Store Instruction LSX_INST 513 WO
Cache Control LSX_CCSR 520 R/W
Vector Module Registers 7–5