Owner`s manual

Table 7–2: FV64A Registers—Vector Indirect Registers

Address (hex) Type

Vector Register 0 VREG0 000–03F R/W

Vector Register 1 VREG1 040–07F R/W

Vector Register 2 VREG2 080–0BF R/W

Vector Register 3 VREG3 0C0–0FF R/W

Vector Register 4 VREG4 100–13F R/W

Vector Register 5 VREG5 140–17F R/W

Vector Register 6 VREG6 180–1BF R/W

Vector Register 7 VREG7 1C0–1FF R/W

Vector Register 8 VREG8 200–23F R/W

Vector Register 9 VREG9 240–27F R/W

Vector Register 10 VREG10 280–2BF R/W

Vector Register 11 VREG11 2C0–2FF R/W

Vector Register 12 VREG12 300–33F R/W

Vector Register 13 VREG13 340–37F R/W

Vector Register 14 VREG14 380–3BF R/W

Vector Register 15 VREG15 3C0–3FF R/W

Arithmetic Instruction ALU_OP 440

R/BW

Scalar Operand Low ALU_SCOP_LO 448 R/BW

Scalar Operand High ALU_SCOP_HI 44C R/BW

Vector Mask Low ALU_MASK_LO 450 BR/BW

Vector Mask High ALU_MASK_HI 451 BR/BW

Exception Summary ALU_EXC 454 R/BW

Diagnostic Control ALU_DIAG_CTL 45C R/BW

Current ALU Instruction VCTL_CALU 480 R/W

Deferred ALU Instruction VCTL_DALU 481 R/W

Addresses from 400–45F in this column specify the address of Verse chip 0; ad-

dresses for Verse chips 1, 2, and 3 are found by adding 1, 2, and 3 to the ad-

dress given. A read must specify each Verse chip by its own address; a write to the ad-

dress given in the table (for Verse chip 0) is broadcast to all Verse chips.

7–4 VAX 6000 Model 500 Mini-Reference