Owner`s manual

Figure 5–7: Memory Control Register 2 (MCTL2)
3
1
1
8
1
7
1
6
1
5 6543210
MUST BE ZERO MUST BE ZER0
Force Memory Refresh (FMRE)
msb−p232−90
Refresh Error (RERR)
Hold Mode (HLDM)
Refresh Rate (RRB)
Arbitration Suppression Mode (ARBSC)
Figure 5–8: TCY Tester Register (TCY)
3
1
3
0 43210
MUST BE ZERO
Ignore Data ECC Check Bits (IDEC)
Ignore Block State ECC Check Bits (IBEC)
TCY Mode (Refresh Enabled) (TCYE)
TCY Mode (XMA Compatible, Refresh Disabled) (TCYD)
msb−p242−90
Block State ECC Test (BSET)
Data ECC Test (ECCT)
Refresh Request (TRR)
MS65A Memory Registers 5–5