VAX 6000 Model 500 Mini-Reference Order Number EK–650EA–HR–001 This manual supplies easy-to-access key information on VAX 6000 Model 500 systems.
First Printing, October 1990 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license.
Contents Preface xi Chapter 1 Console Operation Chapter 2 Self-Test Chapter 3 Address Space 3.1 3.2 How to Find a Register in XMI Address Space . . . . . . . . . . . How to Find a Register in VAXBI Address Space . . . . . . . . . . 3–5 3–6 Chapter 4 KA65A CPU Module Registers 4.1 4.2 4.3 4.4 4.5 KA65A Internal Processor Registers . . KA65A Registers in XMI Private Space KA65A XMI Registers . . . . . . . . . . . . . Machine Checks . . . . . . . . . . . . . . . . . . KA65A Parse Trees . . . . . . . . .
Chapter 7 Vector Module Registers 7.1 7.2 7.3 7.4 7.5 Console Commands to Access Registers . . . . . KA65A IPRs Related to the Vector Module . . FV64A Internal Processor Registers . . . . . . . FV64A Registers — Vector Indirect Registers FV64A Parse Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 . 7–7 . 7–8 . 7–11 .
4–15 4–16 4–17 4–18 4–19 4–20 4–21 4–22 4–23 4–24 4–25 4–26 4–27 4–28 4–29 4–30 4–31 4–32 4–33 4–34 4–35 4–36 4–37 4–38 4–39 4–40 4–41 4–42 4–43 4–44 4–45 4–46 4–47 4–48 4–49 4–50 Backup Cache Status Register (BCSTS) . . . . . . . . . . . . . . . . Backup Cache Control Register (BCCTL) . . . . . . . . . . . . . . . . Backup Cache Error Address Register (BCERA) . . . . . . . . . . Backup Cache Tag Store Register (BCBTS) . . . . . . . . . . . . . . Backup Cache Deallocate Tag Register (BCDET) . . . . . . . .
4–51 Failing DAL Register 3 (FDAL3) . . . . . . . . . . . . . . . . . . . . . . 4–52 Interprocessor Implied Vector Interrupt Generation Register (IPIVINTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53 Write Error Implied Vector Interrupt Generation Register (WEIVINTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–54 Device Register (XDEV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–55 Bus Error Register 0 (XBER0) . . . . . . .
5–18 5–19 6–1 6–2 6–3 6–4 6–5 6–6 6–7 6–8 6–9 6–10 6–11 6–12 6–13 6–14 6–15 6–16 6–17 6–18 6–19 6–20 6–21 6–22 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 7–9 7–10 7–11 EEPROM Control Register (EECTL) . . . . . . . . . . . . . . . . . Timeout Control/Status Register (TMOER) . . . . . . . . . . . . Device Register (XDEV) . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error Register (XBER) . . . . . . . . . . . . . . . . . . . . . . . . Failing Address Register (XFADR) . . . . . . . . . . . . . . . . . . .
7–12 7–13 7–14 7–15 7–16 7–17 7–18 7–19 7–20 7–21 7–22 7–23 7–24 7–25 7–26 7–27 7–28 7–29 7–30 7–31 7–32 7–33 7–34 7–35 7–36 7–37 7–38 7–39 7–40 7–41 7–42 7–43 7–44 7–45 7–46 7–47 viii Vector Register n (VREGn) . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Exception Register (ALU_OP) . . . . . . . . . . . . . Scalar Operand Low Register (ALU_SCOP_LO) . . . . . . . . Scalar Operand High Register (ALU_SCOP_HI) . . . . . . . . Vector Mask Low Register (ALU_MASK_LO) . . . . . . . . . .
7–48 7–49 7–50 7–51 7–52 Translation Buffer PTE Register (LSX_PTE) FV64A Machine Check Parse Tree . . . . . . . . . FV64A Hard Error Interrupt Parse Tree . . . . FV64A Soft Error Interrupt Parse Tree . . . . . FV64A Disable Fault Parse Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27 7–28 7–29 7–30 7–31 VAX 6000 Series Documentation . . . . . . . . . . . . . . . . . . . . .
7–2 x FV64A Registers—Vector Indirect Registers . . . . . . . . . . . . .
Preface Intended Audience This manual is intended for the system manager and programmer.
Table 1 (Cont.
Table 2 (Cont.
Table 2 (Cont.
xvi
Chapter 1 Console Operation This chapter provides reference information for working at the console terminal. Terminal setup characteristics: • The maximum recommended baud rate is 1200. If the console is not responding, you may need to press the Break key to increment the baud rate. • Terminal characteristics should be set to the following: eight bits, no parity, one stop bit.
Figure 1–1: International and English Control Panels 0 FRONT EEPROM 2 1 0 Standby Run Enable Battery Secure Fault Update Halt KEY Auto Start Restart msb-0037A-90 1–2 VAX 6000 Model 500 Mini-Reference
Table 1–1: Upper Key Switch Position Effect Light Color O (Off) Removes all power, except to the battery backup unit and optional storage. No light Standby Supplies power to XMI backplane, blowers, and incabinet console load device. Red Enable Supplies power to whole system; console terminal is enabled. Used for console mode or restart, and to start self-test. Yellow Secure (Normal Position) Prevents entry to console mode; position used while machine is executing programs.
Table 1–4: Control Panel Status Indicator Lights Light Color State Meaning Run Green On System is executing operating system instructions on at least one processor. Off System is in console mode, is set to Standby, or is turned off. On Battery backup unit is charged to 98% of full capacity or battery backup unit is supplying power to the load. Flashing 1 x/sec Battery backup unit is charging. Flashing 10 x/sec Battery backup requires service. Off System does not have a battery backup unit.
Table 1–5 (Cont.): Console Commands and Qualifiers Command and Qualifiers Function EXAMINE /B /G /I /L /M /N /P /Q /V /VE /W Displays the contents of a specified address. FIND /MEMORY /RPB Searches main memory for a page-aligned 256-Kbyte block of good memory or for a restart parameter block. HALT Null command; no action is taken since the processor has already halted in order to enter console mode. HELP Prints explanation of console commands.
Table 1–5 (Cont.): Console Commands and Qualifiers Command and Qualifiers Function SET TERMINAL /BREAK /NOBREAK /HARDCOPY /NOHARDCOPY /SCOPE /NOSCOPE /SPEED:n Sets console terminal characteristics. SHOW ALL Displays the current value of parameters set. SHOW BOOT Displays all boot commands and nicknames that have been saved using SET BOOT. SHOW CONFIGURATION Displays the hardware device type and revision level for each XMI and VAXBI node and indicates self-test status.
Table 1–5 (Cont.): Console Commands and Qualifiers Command and Qualifiers Z Function Logically connects the console terminal to another processor on the XMI bus or to a VAXBI node. /BI:n ! Introduces a comment. Table 1–6: Console Control Characters Character Function BREAK Increments the console baud rate if enabled. CTRL/C Causes the console to abort processing of a command. CTRL/O Causes console to discard output to the console terminal until the next is entered.
BOOT /XMI:m /R5:n /R3:r /NODE: sstt /BI:u /FILENAME:x Figure 1–2: BOOT Command Syntax DDww Invokes BOOT command Selects XMI node Register 5 optional parameters for VMB Register 3 optional unit number information Selects HSC controller on the VAXcluster Selects optional VAXBI boot device adapter Specifies file used to boot system from an NI-based server Selects boot device and hexadecimal unit number msb-0441B-90 Table 1–7: BOOT Command Qualifiers Qualifier Function /X[MI]:number Specifies the XMI
Table 1–7 (Cont.): BOOT Command Qualifiers Qualifier Function This qualifier is used when multiple unit numbers must be specified: for example, when booting from VMS shadow sets. If / R3 is specified, the unit number portion of the device name is ignored. /N[ODE]:number Specifies the remote node(s) that provide access to the boot device. The /XMI (and optionally /BI) qualifiers must have identified a controller that supports "nodes" such as a VAXcluster adapter.
Table 1–9: R5 Bit Functions for VMS Bit Function 0 Conversational boot. The secondary bootstrap program, SYSBOOT, prompts you for system parameters at the console terminal. 1 Debug. If this flag bit is set, the operating system maps the code for the XDELTA debugger into the system page tables of the running operating system. 2 Initial breakpoint. If this flag bit is set, VMS executes a breakpoint (BPT) instruction early in the bootstrapping process. 3 Secondary boot from boot block.
Table 1–11 lists the console error messages that appear when the processor halts and the console gains control.
Table 1–11 (Cont.): Console Error Messages Indicating Halt Error Message Meaning ?0010 ACV/TNV occurred during machine check processing. An access violation or translation-notvalid error occurred while handling another error condition. ?0011 ACV/TNV occurred during kernel-stacknot-valid processing. An access violation or translation-notvalid error occurred while handling another error condition. ?0012 Machine check occurred during machine check processing.
Table 1–12: Standard Console Error Messages Error Message Meaning ?0020 Illegal memory reference. An attempt was made to reference a virtual address (/V) that is either unmapped or is protected against access under the current PSL. ?0021 Illegal command. The command was not recognized, contained the wrong number of parameters, or contained unrecognized or inappropriate qualifiers. ?0022 Illegal address.
Table 1–12 (Cont.): Standard Console Error Messages Error Message Meaning ?002D For Secondary Processor n. This message is a preface to second message describing some error related to a secondary processor. This message indicates which secondary processor is involved. ?002E Specified node is not an I/O adapter. The referenced node is incapable of performing I/O or did not pass its selftest. ?0030 Write to Z command target has timed out. The target node of the Z command is not responding.
Table 1–12 (Cont.): Standard Console Error Messages Error Message Meaning ?003D Error initializing I/O device. A console boot primitive needed to perform I/O, but could not initialize the I/O adapter. ?003E Timeout while sending message to secondary processor. A secondary processor failed to respond to a message sent from the primary. The primary sends such messages to perform console functions on secondary processors. ?003F Microcode power-up self-test failed in REX520.
Table 1–12 (Cont.): Standard Console Error Messages Error Message Meaning ?0048 Uncorrectable memory errors—long memory test must be performed. A Model 400 memory array contains an unrecoverable error. The console must perform a slow test to locate all the failing locations. ?0049 Memory cannot be initialized. The specified operation was attempted and prevented.
Table 1–12 (Cont.): Standard Console Error Messages Error Message Meaning ?0054 EEPROM revision mismatch. Secondary processor has revision x.xx/y.yy. A secondary processor has a different revision of EEPROM or has a different set of EEPROM patches installed. ?0055 Failed to locate EEPROM area. The EEPROM did not contain a set of data required by the console. The EEPROM may be corrupted. ?0056 Console parameters on secondary processor do not match primary.
Table 1–12 (Cont.): Standard Console Error Messages Error Message ?0063 vice. Unable to Meaning locate console tape de- The console could not locate the I/O adapter that controls the TK tape. ?0064 Operation only applies to secondary processors. The command can only be directed at a secondary processor. ?0065 Operation not allowed from secondary processor. A secondary processor cannot perform this operation. ?0066 Validation of EEPROM tape image failed.
Table 1–12 (Cont.): Standard Console Error Messages Error Message Meaning ?0073 System serial number updated. The EEPROM has been updated with the correct system serial number. ?0074 System serial number not updated. The EEPROM has not been changed. ?0075 /CONSOLE_LIMIT value too small for proper operation. Value ignored. No change has been made. ?0076 Error writing to tape. Tape may be write-locked. Tape has not been written. Check to see if tape is write-locked.
Table 1–12 (Cont.): Standard Console Error Messages Error Message Meaning ?0106 Filename cannot contain nested blanks or tabs. For filename specified in a MOP boot. ?0107 Filename can be no longer than 16 characters. For filename specified in a MOP boot. ?0111 Microcode power-up self-test failed in DC595. CPU chip failed its microcoded selftest. ?011E Uncorrectable memory errors discovered long memory test must be performed on node n Memory array in node n contains an uncorrectable error.
Table 1–12 (Cont.): Standard Console Error Messages Error Message ?8029 Bootstrap failed due to previous Meaning error.1 The previous attempt to bootstrap the system failed. ?802A Restart failed due to previous error.1 The previous attempt to restart the system failed. Node n: ?xxxx Error message ?xxxx was generated on secondary processor n and was passed to the primary processor to be displayed. 1 No numbered prefix appears with these messages in English language mode.
6. * Remote service link established 7. * Reading boot image from remote node ?010F Failed to receive image from remote server 8. * Passing control to transfer address Disk Boot Status and Error Boot Messages 1. [Start Boot] ?0046 Specified node is not an I/O adapter ?0100 Specified adapter failed selftest ?010A Illegal adapter specified for disk boot 2. * Initializing adapter ?0119 Failure to initialize specified adapter 3. * Specified adapter initialized successfully 4.
Tape Status and Error Boot Messages 1. [Start boot] ?0046 Specified node is not an I/O adapter ?0100 Specified adapter failed selftest ?010C Illegal adapter specified for tape use 2. * Initializing adapter ?0119 Failure to initialize specified adapter 3. * Specified adapter initialized successfully 4.
?0101 BVP port error—aborting 7. * Passing control to transfer address CI Status and Error Boot Messages 1. [Start boot] ?0046 Specified node is not an I/O adapter ?0109 Illegal adapter specified for CI boot 2. * Initializing adapter ?0119 Failure to initialize specified adapter 3. * Specified adapter initialized successfully 4. * Connecting to storage controller 5. * Previous operation failed—retrying CI boot 6.
?0116 Specified unit is inoperative ?0103 Drive error detected—aborting ?0102 Controller error detected—aborting ?0114 Serious exception reported—aborting 13.
1–26 VAX 6000 Model 500 Mini-Reference
Chapter 2 Self-Test Example 2–1 is a sample self-test display, which deliberately includes some failures to illustrate the type of information reported. Each line is described below. Table 2–1 describes the configuration and assumptions used for this sample. Example 2–1: Sample Self-Test Results, Scalar Processors Only ! #123456789 0123456789 0123456789 0123456789 012345# F ) >>> E D C B A 9 8 7 6 5 4 3 2 1 A + . . . . . . . . A + . . . . . . . . M + . . . M + . . . M + . . .
# $ % The TYP line in the printout indicates the type of module at each node: A = I/O adapter P = scalar processor V = vector processor M = memory module The STF line shows the results of self-test. This information is taken from the self-test fail bit in the XBER register of each module. The entries are: + (pass) – (fail) o (does not apply) The BPD line indicates boot processor designation.
+> +? processor is displayed here, and you receive an error message that your processors have different ROM levels. The EEPROM information gives the boot processor’s version of EEPROM and the patch level. In Example 2–1 the first number, 1.00, gives the version of the contents of the EEPROM, and the second number, 1.00, is the console patch level. If you run processors whose EEPROMs do not match, you will receive an error message. SN gives the system serial number.
Example 2-2 shows a self-test display that contains an additional line when an optional VAXBI adapter (DWMBB) is part of the system configuration. The XBI line provides information on the node numbers and self-test status for modules in the VAXBI card cages, which are connected to the XMI through a DWMBB. Example 2–2: Sample Self-Test Results with VAXBI Adapter #123456789 0123456789 0123456789 0123456789 012345# F . E D C B A 9 8 7 6 5 4 3 2 1 A o . . . . . . . . A + . . . . . . . .
Example 2–3 shows a sample self-test display when a vector processor is included in the system configuration. Example 2–3: Sample Self-Test Results with Vector Processor #123456789 0123456789 0123456789 0123456789 0123456789 # F E D C B A 9 8 7 6 5 4 3 2 A + . . . . . . . . A + . . . . . . . . M + . . . M + . . . . . . . . . . . . . M + . . . V- -P + + E E + + E E M + . . . V- -P + + E B + + E B . . . . . . . . A4 32 A3 32 . . . . A2 32 . . A1 32 . . Console = V1.
Table 2–2 lists each module’s LED status indicating self-test passed or selftest failed.
Self-Test 2–7
Chapter 3 Address Space The design of the hardware for the system bus (the XMI) and for the optional VAXBI bus affects addressing. The XMI card cage has its 14 slots permanently assigned to specific address locations. For the Model 500, no modules that require I/O cables can be installed in the middle four slots (slots 6 through 9). The VAXBI bus consists of two VAXBI card cages that are physically fastened together and logically connected as one 12-slot VAXBI bus.
The XMI supports 2 gigabytes of physical memory space and 512 megabytes of I/O space, as shown in Figure 3–2. Figure 3–2: XMI Memory and I/O Address Space Byte Address 0000 0000 Physical Memory Space (2 Gigabytes) 7FFF FFFF 8000 0000 Unused Space DFFF FFFF E000 0000 I/O Space (512 Megabytes) FFFF FFFF msb−p374−90 Register addresses for a particular device in a system are found by adding an offset to the base address for that particular device.
XMI I/O space is divided into private space, nodespace, and ten I/O adapter address space regions.
XMI Private Space References to XMI private space are serviced by resources local to a node, such as local device CSRs and boot ROM. The references are not broadcast on the XMI. XMI private space is a 24-Mbyte address region located from E000 0000 to E17F FFFF. XMI Nodespace The VAX 6000 platform XMI nodespace is a collection of 16 512-Kbyte regions located from E180 0000 to E1FF FFFF. Nodes 0 and F are not implemented.
3.1 How to Find a Register in XMI Address Space Because XMI addresses correspond to slot and node numbers, you want to determine the slot of the XMI card cage in which the module resides. The slot number can be determined in two ways: • By looking at the XMI card cage (numbering of slots is shown in Figure 3–1) • By entering at the console a SHOW CONFIGURATION command A typical response is shown below.
3.2 How to Find a Register in VAXBI Address Space The first part of a VAXBI adapter’s physical XMI address depends on which XMI slot the DWMBB/A module occupies. The second part of the address depends on the adapter’s VAXBI node number, which is shown in the SHOW CONFIGURATION display. NOTE: VAXBI slot and node numbers are not identical.
2. From Table 3–2 find VAXBI node 4 and in column 2 you can see that the starting address for VAXBI node 4 is xx00 8000. 3. Combine this second number with the two digits. You now have the adapter’s base address (FC00 8000) in VAXBI address space, indicated by lowercase bb. 4. From Table 3–3, VAXBI Registers, you can see that the VAXBI Device Register (DTYPE) is at bb + 00, which is FC00 8000.
Table 3–3: VAXBI Registers Name Mnemonic Address1 Device Register DTYPE bb+00 VAXBI Control and Status Register VAXBICSR bb+04 Bus Error Register BER bb+08 Error Interrupt Control Register EINTRSCR bb+0C Interrupt Destination Register INTRDES bb+10 IPINTR Mask Register IPINTRMSK bb+14 Force-Bit IPINTR/STOP Destination Register FIPSDES bb+18 IPINTR Source Register IPINTRSRC bb+1C Starting Address Register SADR bb+20 Ending Address Register EADR bb+24 BCI Control and Status Re
Address Space 3–9
Chapter 4 KA65A CPU Module Registers The KA65A module registers consist of the following: • Internal processor registers (IPRs) (see Table 4–2) • Registers in XMI private space (see Table 4–3) • XMI registers (see Table 4–4) Machine-check parameters are listed in Section 4.4 and parse trees in Section 4.5.
Table 4–1: Types of Registers, Bits, and Fields Type Description MBZ Must be zero. Bits and fields specified as MBZ must never be filled by software with a nonzero value. If the CPU encounters a nonzero value in a bit or field specified as MBZ, a Reserved Operand Exception occurs. SBZ Should be zero. Bits and fields specified as SBZ should be filled by software with a zero value. If CPU encounters a nonzero value in a bit or field specified as SBZ, UNPREDICTABLE results occur.
4.
Table 4–2 (Cont.
Table 4–2 (Cont.
Table 4–2 (Cont.
Table 4–2 (Cont.
Figure 4–1: Interval Clock Control and Status Register (ICCS) 3 1 7 6 5 MUST BE ZERO 0 MUST BE ZERO Receiver Interrupt Enable (RX IE) msb−p376−90 Figure 4–2: Console Receiver Control and Status Register (RXCS) 3 1 8 7 6 5 MUST BE ZERO 0 MUST BE ZERO Receiver Done (RX DONE) Receiver Interrupt Enable (RX IE) msb−p266−90 Figure 4–3: Console Receiver Data Buffer Register (RXDB) 3 1 1 1 1 1 1 1 1 6 5 4 3 2 1 0 MUST BE ZERO 0 8 7 0 MBZ Error (ERR) Overrun Error (OVR ERR) Framing Error (FRM ERR) Rece
Figure 4–4: Console Transmitter Control and Status Register (TXCS) 3 1 8 7 6 5 MUST BE ZERO 3 2 1 0 MBZ 0 Transmitter Ready (TX RDY) Transmitter Interrupt Enable (TX IE) Loopback Transmit Break (XMIT BRK) msb−p268−90 Figure 4–5: Console Transmitter Data Buffer Register (TXDB) 3 1 8 7 0 MUST BE ZERO Transmit Data msb−p269−90 Figure 4–6: Machine Check Error Summary Register (MCESR) 3 1 0 Machine Check Error Summary Register (MCESR) msb−p270−90 KA65A CPU Module Registers 4–9
Figure 4–7: Accelerator Control and Status Register (ACCS) 3 3 1 0 3 2 1 0 MUST BE ZERO Write Even Parity Addressing Mode (ADRM) F−Chip Present Vector Present msb−p271−90 Figure 4–8: Console Saved Program Counter Register (SAVPC) 3 1 0 Console Saved Program Counter (SAVPC) msb−p272−90 Figure 4–9: Console Saved Processor Status Longword (SAVPSL) 3 1 1 1 1 1 6 5 4 3 8 7 0 Processor Status Longword<31:16> (PSL<31:16>) Memory Management Enable (MAPEN<0>) Invalid Halt Code Processor Status Longword<7:0>
Figure 4–10: Translation Buffer Tag Register (TBTAG) 3 1 9 8 Virtual Page Number (VPN) 0 MUST BE ZERO msb−p274−90 Figure 4–11: I/O Reset Register (IORESET) 3 1 0 IORESET msb−p275−90 Figure 4–12: Translation Buffer Data Register (TBDATA) 3 3 1 0 2 2 2 7 6 5 2 2 3 2 0 MBZ Page Table Entry Page Frame Number (PTE.PFN) Page Table Entry Modify (PTE.M) Page Table Entry Protection (PTE.PROT) Page Table Entry Valid (PTE.
Figure 4–13: System Identification Register (SID) 3 1 2 2 4 3 1 1 6 5 8 7 0 MUST BE ZERO CPU Type Microcode Options Microcode Revision msb−p277−90 Figure 4–14: Backup Cache Index Register (BCIDX) 3 1 1 1 9 8 1 1 1 0 MUST BE ZERO 7 6 0 MBZ Backup Tag Store Row Index (BTS ROW INDEX) Backup Tag Store Column Index (BTS COL INDEX) msb−p281−90 Op 4–12 VAX 6000 Model 500 Mini-Reference
Figure 4–15: Backup Cache Status Register (BCSTS) 3 3 2 2 2 2 2 1 0 9 8 7 6 5 MBZ 2 2 2 1 1 1 1 1 1 2 1 0 9 8 7 6 5 4 9 8 7 6 5 4 3 2 1 0 MBZ 0 Error Summary (ERR SUMMARY) Backup Tag Store Tag Parity Error (BTS TPERR) Backup Tag Store Valid/ Dirty Parity Error (BTS VDPERR) Invalidate Parity Error<1:0> (I PERR<1:0>) Fill Abort Address/Command Parity Error (AC PERR) Second Error (SECOND ERR) Backup Tag Store Hit (BTS HIT) Backup Tag Store Compare (BTS COMPARE) Predicted Parity Generator (PPG) Backup Tag
Figure 4–17: Backup Cache Error Address Register (BCERA) 3 1 3 2 Error Address 0 MBZ msb−p279−90 Figure 4–18: Backup Cache Tag Store Register (BCBTS) 3 3 1 0 0 1 1 9 8 Cache Entry Tag 1 0 9 8 7 4 3 0 MUST BE ZERO Tag Parity Valid/Dirty Parity Dirty bits (D4:D1) Valid bits (V4:V1) msb−p278−90 Figure 4–19: Backup Cache Deallocate Tag Register (BCDET) 3 1 1 0 MUST BE ZERO Backup Cache Deallocate Tag msb−p280−90 4–14 VAX 6000 Model 500 Mini-Reference
Figure 4–20: Backup Cache Error Tag Register (BCERT) 3 3 1 0 1 1 9 8 0 1 0 9 8 7 4 3 0 MUST BE ZERO Backup Cache Entry Tag Tag Parity V/D Parity Dirty<3:0> Valid<3:0> msb−p284−90 Figure 4–21: Vector Interface Error Status Register (VINTSR) 3 1 1 1 1 2 1 0 9 8 7 6 5 4 3 2 1 0 MUST BE ZERO Force Bad Command Parity Force Bad Data Parity Disable Vector Interface (DISABLE VECT INTF) Vector Module Reset Bus Timeout C−Chip VIB Hard Error (CCHIP VIB HERR) C−Chip VIB Soft Error (CCHIP VIB SERR) VECTL VIB H
Figure 4–22: Primary Cache Tag Array Register (PCTAG) 3 3 1 0 1 1 1 0 Tag 1 0 MUST BE ZERO Parity Valid msb−p312−90 Figure 4–23: Primary Cache Index Register (PCIDX) 3 1 1 1 1 0 3 2 MUST BE ZERO 0 MBZ Tag Array Index msb−p311−90 Figure 4–24: Primary Cache Error Address Register (PCERR) 3 1 0 Primary Cache Error Address Register (PCERR) msb−p286−90 4–16 VAX 6000 Model 500 Mini-Reference
Figure 4–25: Primary Cache Status Register (PCSTS) 3 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 MUST BE ZERO 0 Backup Cache Hit (B CACHE HIT) DAL Bus Error (BUS ERROR) Primary Data Parity Error (P DATA PARITY ERROR) DAL Bus Data Parity Error (DAL DATA PARITY ERROR) Tag Parity Error Trap1 Trap2 Interrupt Primary Cache Hit (P CACHE HIT) Flush Cache Enable Primary Tag Store (ENABLE PTS) Force Hit msb−p285−90 KA65A CPU Module Registers 4–17
4.
Table 4–3 (Cont.
Figure 4–27: Control Register 1 (CREG1) 3 1 8 7 6 5 4 3 2 1 0 MUST BE ZERO Self−Test Self−Test Self−Test Self−Test Self−Test Self−Test Self−Test Self−Test LED LED LED LED LED LED LED LED 8 7 6 5 4 3 2 1 (ST (ST (ST (ST (ST (ST (ST (ST LED8) LED7) LED6) LED5) LED4) LED3) LED2) LED1) msb−p314−90 Figure 4–28: Control Register Write Enable (CREGWE) 3 1 0 Control Register Write Enable (CREGWE) WO msb−p008−89 Figure 4–29: MSSC Base Address Register (SSCBAR) 3 3 2 2 1 0 9 8 MBZ 1 1 1 1 0 MSSC Base Addres
Figure 4–30: MSSC Configuration Register (SSCCNR) 3 3 1 0 2 2 2 2 2 2 2 8 7 6 5 4 3 2 MBZ 0 2 1 1 0 9 8 1 1 1 6 5 4 0 1 1 1 2 1 0 8 7 6 MBZ 4 3 2 0 0 CREG Address Enable (CREG ADS ENA) EEPROM Enable (EEPROM ADS ENA) Console Terminal Baud Rate Select (TERM BAUD SEL) CTRL/P Enable (CTRL/P ENA) ROM Halt Protect Address Space Size (HALT PROT) ROM Address Space Size Select (ROM SIZE) ROM Speed Interrupt Priority Level Select (IPL SEL) Interrupt Vector Disable (IV Disable) Battery Low (BLO) msb−p323R−9
Figure 4–32: MSSC Output Port Register (OPORT) 3 1 1 0 9 2 1 0 MUST BE ZERO Control Register Data (CREG DATA) Control Register 1 Select (CREG1 SEL) Control Register 0 Select (CREG0 SEL) msb−p325−90 Figure 4–33: MSSC Input Port Register (IPORT) 3 3 1 0 9 8 7 6 5 4 3 0 MUST BE ZERO Console Enable Scan Test Disable Self−Test Loop Disable (STL DISABLE) XMI AC LO State (XACLO) Front Panel EEPROM Enable (FP EEPROM ENABLE) Front Panel Boot Disable (FP BOOT DISABLE) Node Identification (NODE ID) msb−p326−90
Figure 4–35: Control Register Address Decode Mask Register (CRADMR) 3 3 2 1 0 9 MBZ 2 1 0 Control Register Address Decode Mask (CRADM) MBZ msb−p328−90 Figure 4–36: EEPROM Base Address Register (EEBADR) 3 3 2 1 0 9 MBZ 2 1 0 EEPROM Base Address (EEBAD) MBZ msb−p329−90 Figure 4–37: EEPROM Address Decode Mask Register (EEADMR) 3 3 2 1 0 9 MBZ 2 1 0 EEPROM Address Decode Mask Register (EEADMR) MBZ msb−p330−90 KA65A CPU Module Registers 4–23
Figure 4–38: Timer Control Register 0 (TCR0) 3 3 1 0 8 7 6 5 4 MUST BE ZERO Error (ERR) 2 0 0 0 Interrupt (INT) Interrupt Enable (IE) Single (SGL) Transfer (XFR) Stop (STP) Run (RUN) msb−p331−90 Figure 4–39: Timer Interval Register 0 (TIR0) 3 1 0 Timer Interval Register msb−p332−90 Figure 4–40: Timer Next Interval Register (TNIR0) 3 1 0 Timer Next Interval Register msb−p333−90 4–24 VAX 6000 Model 500 Mini-Reference
Figure 4–41: Timer Interrupt Vector Register (TIVR0) 3 1 10 9 2 1 0 MUST BE ZERO MBZ SCB Vector Offset msb−p334−90 Figure 4–42: Timer Control Register 1 (TCR1) 3 3 1 0 8 7 6 5 4 MUST BE ZERO Error (ERR) 2 0 0 0 Interrupt (INT) Interrupt Enable (IE) Single (SGL) Transfer (XFR) Stop (STP) Run (RUN) msb−p331−90 Figure 4–43: Timer Interval Register (TIR1) 3 1 0 Timer Interval Register msb−p332−90 KA65A CPU Module Registers 4–25
Figure 4–44: Timer Next Interval Register 1 (TNIR1) 3 1 0 Timer Next Interval Register msb−p333−90 Figure 4–45: Timer Interrupt Vector Register 1 (TIVR1) 3 1 10 9 2 1 0 MUST BE ZERO MBZ SCB Vector Offset msb−p334−90 Figure 4–46: MSSC Interval Counter Register (SSCICR) 3 1 1 1 3 2 MUST BE ZERO 0 Current Count msb−p335−90 4–26 VAX 6000 Model 500 Mini-Reference
Figure 4–47: DAL Diagnostic Register (DCSR) 3 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 8 7 6 5 4 3 0 MUST BE ZERO Diagnostic MDA XMI XMIP<1:0> (FXMIP<1:0>) Enable Force MDA XMI Parity (EFXMIP) Write Data Parity Check Disable (WDPCD) Diagnostic DP Value (FDP) Diagnostic ECC<5:0> Value (FECC<5:0>) Writeback ECC Check Disable (WBECCD) Read Upper Longword (RUP) Enable Force DP (EFDP) Enable Force (EFECC) MDA Revision (MDAREV) msb−p336−90 Figure 4–48: Failing DAL Register 0 (FDAL0) 3 1 0 DAL<31:0> msb−p337−90 Figure
Figure 4–50: Failing DAL Register 2 (FDAL2) 3 1 0 ECC<31:0> msb−p339−90 Figure 4–51: Failing DAL Register 3 (FDAL3) 3 1 2 2 4 3 MUST BE ZERO 1 1 6 5 0 DP<7:0> ECC<47:32> msb−p340−90 Figure 4–52: Interprocessor Implied Vector Interrupt Generation Register (IPIVINTR) 3 1 1 1 6 5 MUST BE ZERO 0 IPIVINTR Destination Mask msb−p341−90 4–28 VAX 6000 Model 500 Mini-Reference
Figure 4–53: Write Error Implied Vector Interrupt Generation Register (WEIVINTR) 3 1 1 1 6 5 MUST BE ZERO 0 WEIVINTR Destination Mask msb−p342−90 KA65A CPU Module Registers 4–29
4.
Figure 4–55: Bus Error Register 0 (XBER0) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 3 FCID 0 MBZ Reserved Failing Commander ID Self−Test Fail (STF) Extended Test Fail (ETF) Node−Specific Error Summary (NSES) Commander Errors Transaction Timeout (TTO) Reserved; must be zero Command NO ACK (CNAK) Read Error Response (RER) Read Sequence Error (RSE) No Read Response (NRR) Corrected Read Data (CRD) Write Data NO ACK
Figure 4–56: Failing Address Register (XFADR0) 3 1 2 1 0 9 1 1 6 5 0 MUST BE ZERO Interrupt Priority Level (IPL) Interrupt Source msb−p346−90 Figure 4–57: XMI General Purpose Register (XGPR) 3 1 0 XMI General Purpose Register (XGPR) msb−p201−89 Figure 4–58: Node Specific Control and Status Register (NSCSR0) 3 1 1 1 1 0 7 6 5 4 3 0 MUST BE ZERO High Drive Output Disable (DHOD) Boot Processor Disable (BPD) Boot Processor (BP) Warm Start (WS) MCA Revision (MCAREV) msb−p348−90 4–32 VAX 6000 Model 50
Figure 4–59: XMI Control Register 0 (XCR0) 3 3 2 2 2 2 2 1 0 9 8 7 6 5 2 2 2 1 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 MBZ 0 MBZ REQUIRED Lockout Mode (LOCMOD) XMI BAD Drive (XBADD) Trigger Control (TRIGC) Corrected Read Interrupt Disable (CRDID) Corrected Confirmation Interrupt Disable (CCID) MSSC IPL<1:0> (MSCIPL) XMI−RELATED Lockout Debug Timeout Enable (LDTE) LED Control (LEDC) Vector Mode Enable (VME) Timeout Select (TOS) Enable Self Invalidates Only (ESIO) XMI Force Parity<2:
Figure 4–61: Bus Error Extension Register 0 (XBEER0) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 0 3 2 1 0 MBZ REQUIRED Second Error Occurred (SEO) Only LOC Response (OLR) Unexpected Read Response (URR) XMI−RELATED Unexpected Unlock Write (UUW) MCA−Chip XMI Parity Error (MCAXPE) MDA−Chip XMI Parity Error (MDAXPE) Unlock Write Pending (UWP) WRITEBACK−RELATED WBack1 WBack1 WBack1 WBack1 WBack1 WBack1 WBack1 WBack1 WBack0 Failing DAL Qualifier (WFDQ0) WBack
Figure 4–62: Writeback 0 Failing Address Register (WFADR0) 3 3 2 2 2 1 0 9 8 7 0 X D2 4 4 2 2 M 9 9 8 8 7 I 0 Failing Writeback Address Failing Writeback Address Extension msb−p351−90 Figure 4–63: Writeback 1 Failing Address Register (WFADR1) 3 3 2 2 2 1 0 9 8 7 0 X D2 4 4 2 2 M 9 9 8 8 7 I 0 Failing Writeback Address Failing Writeback Address Extension msb−p351−90 KA65A CPU Module Registers 4–35
4.4 Machine Checks A machine check exception is reported through SCB vector 04 (hex) when an error condition is detected. The frame pushed on the stack for a machine check indicates the type of error and provides internal state information that helps to identify the cause of the error. The machine check stack frame is shown in Figure 4–64 and its parameters are described in Table 4–5. Table 4–6 lists and describes the machine check codes.
Table 4–5: Machine Check Parameters Parameter Description Parameter Byte Count The size of the stack frame in bytes, not including PSL, PC, and the byte count longword. It is always 18 (hex) bytes. Stack frame PC and PSL values are always referenced using this count as an offset from the stack pointer. R (VAX Restart bit) A flag from the hardware and microcode to the operating system to be used in the software equation to determine if the current macroinstruction is restartable after error cleanup.
Table 4–5 (Cont.): Machine Check Parameters Parameter Description AT. bits<20:18> DL, bits<17:16> Opcode, bits<15:8> The current setting of the E-box (the MP-chip’s execution unit or main data path) access-type latch, relating to the last (or upcoming) memory reference.
Table 4–5 (Cont.): Machine Check Parameters Parameter Description RN, bits<3:0> The value of the E-box RN ter at the time of the fault, may indicate the last GPR enced by the E-box during fier or instruction flows. regiswhich referspeci- SC Internal microcode-accessible register. PC, PSL The program counter and processor status longword at the time of the fault.
Table 4–6 (Cont.): Machine Check Codes Code (hex) Mnemonic and Description Restart Condition 09 MCHK_TBM_ACV_TNV Translation buffer hit status generated in ACV/TNV microflow ((R=1)+(FPD=1)).(UWP=0) 0A MCHK_INT_TD_VALUE Undefined INT.ID value during interrupt service ((R=1)+(FPD=1)).(UWP=0) 0B MCHK_MOVC_STATUS Undefined state bit combination in MOVCx (FPD=1).
4.
Figure 4–65 (Cont.
Figure 4–65 (Cont.
Figure 4–65 (Cont.
Figure 4–65 (Cont.
Figure 4–66: KA65A Hard Error Interrupt Parse Tree Figure 4–66 Cont’d on next page 4–46 VAX 6000 Model 500 Mini-Reference
Figure 4–66 (Cont.
Figure 4–66 (Cont.
Figure 4–67: KA65A Soft Error Interrupt Parse Tree (select all) PCSTS (PCSTS<5>) (select all) PCSTS (PCSTS<8>) P−cache tag parity error on read, write, or invalidate PCSTS (PCSTS<10>) P−cache data parity error on I−stream read hit PCSTS (PCSTS<9>) (select one) PCSTS (PCSTS<12>) Backup cache data parity error on I−stream read or nonrequested longword of D−stream read otherwise MAXMI data parity error on I−stream read or n
Figure 4–67 (Cont.
Chapter 5 MS65A Memory Registers Table 5–1: MS65A Memory Control and Status Registers Name Mnemonic Address Device Register XDEV BB1 + 00 Bus Error Register XBER BB + 04 Starting and Ending Address Register SEADR BB + 10 Memory Control Register 1 MCTL1 BB + 14 Memory ECC Error Register MECER BB + 18 Memory ECC Error Address Register MECEA BB + 1C Memory Control Register 2 MCTL2 BB + 30 TCY Tester Register TCY BB + 34 Block State ECC Error Register BECER BB + 38 Block State EC
Figure 5–1: Device Register (XDEV) 3 1 2 2 4 3 1 1 6 5 8 7 0 MUST BE ZERO Device Revision (DREV) Device Class (DCLS) Device ID (DEVID) msb−p245−90 Figure 5–2: Bus Error Register (XBER) 3 3 2 2 2 2 1 0 9 8 7 6 0 0 2 2 2 2 2 4 3 2 1 0 MBZ 1 1 1 1 3 2 1 0 9 MUST BE ZERO 0 0 MUST BE ZERO Self−Test Completed (STC) Node−Specific Error Summary (NSES) Read Data NO ACK (RDNAK) Write Sequence Error (WSE) Bus Parity Error (BPE) Corrected Confirmation Received (CCR) Node Reset (NRST) Error Summary (ES) msb−p
Figure 5–3: Starting and Ending Address Register (SEADR) 3 3 2 2 1 0 9 8 MBZ 2 2 4 3 1 1 6 5 1 1 1 0 MUST BE ZERO 8 7 6 5 4 MBZ 2 1 0 MBZ Top 512 MByte Ending Address Ending Address (TENADR) (ENADR) Starting Address (STRADR) Interleave Address (INADn) Interleave Address Mode (INTMn) msb−p237−90 Figure 5–4: Memory Control Register 1 (MCTL1) 3 3 2 2 1 0 9 8 1 1 1 1 1 1 1 1 1 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 MBZ C C C C C C C C 7 6 5 4 3 2 1 0 Data Check Bits (DCKB) Data RMWrite Error (DRMWER
Figure 5–5: Memory ECC Error Register (MECER) 3 3 2 2 2 2 2 2 1 0 9 8 7 6 5 4 0 2 2 2 1 1 1 6 5 1 1 2 1 MBZ 8 7 0 MBZ Data Commander Syndrome Code (COMCD) (DTSYN) Commander ID (COMID) Column Parity Error (Data Address) (CPER) Row Parity Error (Data Address) (RPER) Byte Write Error (Data Address) (BWERR) Data CRD Error (DCRDE) Second Data Error Occurred (SDEO) Data RER Error (DRER) msb−p236−90 Figure 5–6: Memory ECC Error Address Register (MECEA) 3 1 3 2 DATA ERROR ADDRESS (DERA) 0 MBZ msb−p235−9
Figure 5–7: Memory Control Register 2 (MCTL2) 3 1 1 1 1 1 8 7 6 5 MUST BE ZERO 6 5 4 3 2 1 0 MUST BE ZER0 Force Memory Refresh (FMRE) Refresh Error (RERR) Hold Mode (HLDM) Refresh Rate (RRB) Arbitration Suppression Mode (ARBSC) msb−p232−90 Figure 5–8: TCY Tester Register (TCY) 3 3 1 0 4 3 2 1 0 MUST BE ZERO Ignore Data ECC Check Bits (IDEC) Ignore Block State ECC Check Bits (IBEC) Block State ECC Test (BSET) Data ECC Test (ECCT) Refresh Request (TRR) TCY Mode (Refresh Enabled) (TCYE) TCY Mode (XMA Com
Figure 5–9: Block State ECC Error Register (BECER) 3 3 2 2 2 2 2 2 2 2 2 1 0 9 8 7 6 5 4 3 2 1 0 1 1 6 5 1 1 1 2 1 0 9 8 7 6 5 4 MBZ 0 0 Block Syndrome (BSYN) Block State ID (BSID) Block State Code (BLSC) Commander Code (COMCD) Commander ID (COMID) Tagged Bad Block Accessed (TBBA) Column Parity Error (CPER) Row Parity Error (RPER) Byte Write Error (BWERR) Block State Correctable Error (BSCE) Second Block State Error Occurred (SBSEO) Block State Uncorrectable Error (BSUE) msb−p224−90 Figure 5–10: Bloc
Figure 5–11: Starting Address Register (STADR) 3 1 1 1 6 5 6 5 0 MUST BE ZERO MBZ Starting Address (STADD) msb−p241−90 Figure 5–12: Ending Address Register (ENADR) 3 1 1 1 1 7 6 5 6 5 0 MUST BE ZERO MBZ Top of Segment Memory Ending Address (TSMEA) Ending Address (ENADD) msb−p228−90 Figure 5–13: Segment/Interleave Register (INTLV) 3 1 2 2 1 0 MUST BE ZERO 1 1 6 5 8 7 6 5 4 MUST BE ZERO Segment Address (SEGADR) 1 0 MBZ Interleave Mode (INMD) Interleave Address (INAD) msb−p230−90 MS65A M
Figure 5–14: Memory Control Register 3 (MCTL3) 3 3 2 2 2 2 1 0 9 8 7 6 1 1 1 6 5 4 0 0 0 Trigger Configuration Mode (TRCM) Trigger Enable (TREN) Inconsistency Errors (INCE) Attempted Invalid EEPROM Update (AIEU) EEPROM Update Enable (EEUE) MCTL3 Error Summary (ERRSM) msb−p233−90 Figure 5–15: Memory Control Register 4 (MCTL4) 3 3 2 2 1 0 9 8 2 2 3 2 MBZ 1 1 1 1 1 1 1 1 1 8 7 6 5 4 3 2 1 0 9 8 5 4 0 MBZ Block ECC Check Bits (BSEC) Block State ID (BSID) Block State Code (BSCD) Ownership Sequence Error
Figure 5–16: Block State Control Register (BSCTL) 3 3 2 2 1 0 9 8 1 1 1 0 9 8 5 4 0 MUST BE ZERO Block State ECC Check Bits (BSEC) Block Commander ID (BSID) Block State (BSTA) Block State Access Mode (BSAM) Block State Port Enable (BSPE) msb−p226−90 Figure 5–17: Block State Address Register (BSADR) 3 1 5 4 BLOCK ADDRESS A (BLAA) 0 MBZ msb−p225−90 MS65A Memory Registers 5–9
Figure 5–18: EEPROM Control Register (EECTL) 3 3 2 1 0 9 2 2 7 6 1 1 6 5 MBZ 8 7 0 MUST BE ZERO EEPROM Data (EEDAT) EEPROM Address (EEADD) EEPROM Operation Command (EEOC) Initiate EEPROM Operation (IEEO) msb−p227−90 Figure 5–19: Timeout Control/Status Register (TMOER) 3 3 2 2 1 0 9 8 1 1 1 6 5 4 MUST BE ZERO Deferred Write Time− Out Occured (DWTO) Deferred Read Time− Out Occured (DRTO) 1 0 MUST BE ZERO Time−Out Counter Mode (TOCM) Time−Out Counter Disable (TOCD) Second Time−Out Occured (STOC) Ti
Chapter 6 DWMBB Adapter Registers The DWMBB adapter consists of two modules: an XMI module in the XMI card cage and a VAXBI module in the VAXBI card cage. Table 6–1 lists the DWMBB registers: some of which are XMI required registers, some DWMBB/A registers, some DWMBB/B registers, and the VAXBI Device Register for the DWMBB/B module. Register addresses for a particular device in a system are found by adding an offset to the base address for that device.
Table 6–1: DWMBB Registers Name Mnemonic1 Address2 Device Register XDEV BB + 00 Bus Error Register XBER BB + 04 Failing Address Register XFADR BB + 08 Responder Error Address Register AREAR BB + 0C DWMBB/A Error Summary Register AESR BB + 10 Interrupt Mask Register AIMR BB + 14 Implied Vector Interrupt Destination/Diagnostic Register AIVINTR BB + 18 Diag 1 Register ADG1 BB + 1C Utility Register AUTLR BB + 20 Control and Status Register ACSR BB + 24 Return Vector Register AR
Table 6–1 (Cont.): DWMBB Registers Name Mnemonic1 Address2 Diagnostic Control Register 1 BDCR1 BB + 58 Reserved Register – BB + 5C Page Map Register (first location) PMR BB + 200 . . . . . .
Figure 6–2: Bus Error Register (XBER) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 3 2 1 0 FCID 0 0 MBZ Reserved Timeout Disabled Reserved Failing Commander ID Self−Test Fail (STF) Reserved Node−Specific Error Summary (NSES) Commander Errors −−−−−−−−−−−−−−−−−−−−−−−−−−−−− Transaction Timeout (TTO) Reserved Command NO ACK (CNAK) Read Error Response (RER) Read Sequence Error (RSE) No Read Response (NRR) Corrected Rea
Figure 6–3: Failing Address Register (XFADR) 3 3 2 1 0 9 0 Failing Address Failing Length (FLN) msb−p102−89 Figure 6–4: Responder Error Address Register (AREAR) 3 3 2 1 0 9 0 Responder Failing Address Responder Failing Length (RFLN) msb−p104−89 DWMBB Adapter Registers 6–5
Figure 6–5: DWMBB/A Error Summary Register (AESR) 3 3 1 0 2 2 6 5 MBZ 2 1 0 9 RFID 1 1 1 1 1 1 1 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 RFCMD 0 DWMBB Cable OK Responder Failing Commander ID Responder Failing Command DWMBB/A Multiple Errors (ME) Correctable PMR ECC Error (CORR PMR ECC ERR) Uncorrectable PMR ECC Error (UNCORR PMR ECC ERR) Invalid PFN (IPFN) Correctable DMA ECC Error (CORR DMA ECC ERR) Uncorrectable DMA ECC Error (UNCORR DMA ECC ERR) Invalid VAXBI Address (INV BI ADR) Internal Error (IE) I/O W
Figure 6–6: Interrupt Mask Register (AIMR) 3 3 1 0 2 2 2 8 7 6 MBZ MBZ INTR CC INTR INTR INTR INTR INTR IPE PE WSE RIDNAK WDNAK 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Enable IVINTR Transactions INTR CRD INTR NRR INTR RSE INTR RER INTR CNAK/NXM RESERVED INTR TTO RESERVED INTR IPFN INTR CORR ECC ERR INTR UNCORR ECC ERR INTR INV BI ADR INTR IE INTR IO WRT FAIL INTR BCI AC LO INTR DMAA DATA PE INTR DMAA CA PE INTR DMAB DATA PE INTR DMAB CA PE INTR I/O RD PE msb−p1
Figure 6–8: Diag 1 Register (ADG1) 3 3 2 2 2 2 2 1 0 9 8 7 6 5 1 1 1 1 1 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Diagnostic ECC Force Illegal Command Force Data NO ACK Error Summary Test Transmit Lockout Status Receive Lockout Status Auto Retry Disable Substitute ECC Latch Check Bits Force ECC Error Force TLOCKOUT Flip FADDR Bit<1> Flip ADR Bit<29> DWMBB Loopback Enable Force Octaword Transfers Force DMAA Buffer Busy Force DMAB Buffer Busy Force Bad IBUS Receive Parity Force Bad IBUS Transmit Parity Interrupt Sent
Figure 6–10: Control and Status Register (ACSR) 3 3 2 2 1 0 9 8 0 1 1 7 6 ECC Syndrome 1 0 9 8 7 6 5 4 3 2 1 0 MUST BE ZERO 0 0 0 PMR Ready Control Reset (CTL RESET) Short Timeout Enable (SHORT TMO ENA) Lockout Response Enable (LOCKOUT RESPONSE ENA) Lockout Assert Enable (LOCKOUT ASSERT END) VAXBI Window Space Enable (BIWIN ENA) Responder Request Enable (RES REQ ENA) Multiple Interrupt Enable (ME ENA) Return Vector Disable (RETURN VECTOR DIS) msb−p109−89 Figure 6–11: Return Vector Register (ARVR) 3 1
Figure 6–12: Failing Address Extension Register (XFAER) 3 1 2 2 2 2 8 7 6 5 FCMD 1 1 6 5 MBZ 0 Failing Mask Failing Address Extension Failing Command msb−p103−89 Figure 6–13: BI Error Address Register (ABEAR) 3 3 2 1 0 9 0 Failing VAXBI Address VAXBI Failing Address Length (BI FLN) msb−p111−89 6–10 VAX 6000 Model 500 Mini-Reference
Figure 6–14: Control and Status Register (BCSR) 3 3 1 0 5 4 3 2 1 0 MUST BE ZERO 0 VAXBI BAD VAXBI Interlock Read Failed Mask VAXBI Power−Up LED IBUS Parity Error Interrupt Mask Enable DWMBB Interrupts (to XMI processor(s)) msb−p113−89 Figure 6–15: DWMBB/B Error Summary Register (BESR) 3 1 1 1 7 6 1 1 1 3 2 1 8 7 6 5 4 3 2 1 0 MUST BE ZERO Interrupt Sent Status DWMBB Interrupt−Pending Status VAXBI Interrupt−Pending Status Multiple CPU Errors Command/Address Fetch Failed Slave Sequencer Transaction
Figure 6–16: Interrupt Destination Register (BIDR) 3 1 1 1 6 5 Diagnostic Read/Write 0 Interrupt Destination msb−p115−89 Figure 6–17: Timeout Address Register (BTIM) 3 3 2 1 0 9 0 VAXBI DMA Failing Address Length msb−p116−89 Figure 6–18: Vector Offset Register (BVOR) 3 1 1 1 6 5 MUST BE ZERO 9 8 0 MUST BE ZERO DWMBB/B Vector Offset Register (VOR) msb−p117−89 6–12 VAX 6000 Model 500 Mini-Reference
Figure 6–19: Vector Register (BVR) 3 1 1 1 6 5 MUST BE ZERO 2 1 0 DWMBB Vector MBZ msb−p118−89 Figure 6–20: Diagnostic Control Register 1 (BDCR1) 3 1 7 6 5 4 3 2 1 0 MUST BE ZERO DWMBB DWMBB Force Force 0 MBZ Flip FADDR Bit<1> Flip Bit<29> BIIC Loopback Mode BCI Bad Parity msb−p119−89 Figure 6–21: Page Map Register (PMR) 3 3 2 1 0 9 2 2 6 5 0 PAGE FRAME NUMBER (PFN) MSB for 40−Bit Address Translation (8KB pages) MSB for 40−Bit Address Translation (4KB pages) MSB for 40−Bit Address Translation (5
Figure 6–22: VAXBI Device Register (DTYPE) 3 1 1 1 6 5 Device Revision 0 Device Type (210F) msb−p121−89 6–14 VAX 6000 Model 500 Mini-Reference
Chapter 7 Vector Module Registers The vector module registers consist of the following: • Internal processor registers (IPRs) (see Table 7–1) • Vector indirect registers (see Table 7–2) • Vector Length, Vector Count, and Vector Mask control registers This chapter explains how to access the registers and then shows the registers. See your System Technical User’s Guide for complete descriptions of the registers. 7.
Figure 7–1: Vector Length (VLR) and Vector Count (VCR) Registers 6 0 msb−p320−90 Figure 7–2: Vector Mask Register (VMR) 6 3 3 2 Vector Mask High Vector Mask Low 3 1 0 msb−p321−90 7–2 VAX 6000 Model 500 Mini-Reference
Table 7–1: Internal Processor Registers Register Mnemonic Address decimal (hex) Type Class Vector Copy—P0 Base P0BR 8 (8) WO 1 Vector Copy—P0 Length P0LR 9 (9) WO 1 Vector Copy—P1 Base P1BR 10 (A) WO 1 Vector Copy—P1 Length P1LR 11 (B) WO 1 Vector Copy—System Base SBR 12 (C) WO 1 Vector Copy—System Length SLR 13 (D) WO 1 Accelerator Control and Status ACCS 40 (28) R/W 2I Vector Copy—Memory Management Enable MAPEN 56 (38) WO 1 Vector Copy—Translation Buffer Invali
Table 7–2: FV64A Registers—Vector Indirect Registers Register Mnemonic Register Field Address (hex) Type Vector Register 0 VREG0 000–03F R/W Vector Register 1 VREG1 040–07F R/W Vector Register 2 VREG2 080–0BF R/W Vector Register 3 VREG3 0C0–0FF R/W Vector Register 4 VREG4 100–13F R/W Vector Register 5 VREG5 140–17F R/W Vector Register 6 VREG6 180–1BF R/W Vector Register 7 VREG7 1C0–1FF R/W Vector Register 8 VREG8 200–23F R/W Vector Register 9 VREG9 240–27F R/W Vec
Table 7–2 (Cont.
Table 7–2 (Cont.
7.
7.
Figure 7–7: Vector Memory Activity Check Register (VMAC) 3 1 0 Vector Memory Activity Check Register msb−p124−90 Figure 7–8: Vector Translation Buffer Invalidate All Register (VTBIA) .
Figure 7–10: Vector Indirect Data Low Register (VIDLO) 3 1 0 Vector Indirect Data Low Register msb−p127−90 Figure 7–11: Vector Indirect Data High Register (VIDHI) 3 1 0 Vector Indirect Data High Register msb−p128−90 7–10 VAX 6000 Model 500 Mini-Reference
7.4 FV64A Registers — Vector Indirect Registers Figure 7–12: Vector Register n (VREGn) 6 3 0 Element 0 : : : . . .
Figure 7–14: Scalar Operand Low Register (ALU_SCOP_LO) 3 1 0 Scalar Operand Low Register msb−p140−90 Figure 7–15: Scalar Operand High Register (ALU_SCOP_HI) 3 1 0 Scalar Operand High Register msb−p141−90 Figure 7–16: Vector Mask Low Register (ALU_MASK_LO) 3 1 0 Vector Mask Low Register msb−p142−90 7–12 VAX 6000 Model 500 Mini-Reference
Figure 7–17: Vector Mask High Register (ALU_MASK_HI) 3 1 0 Vector Mask High Register msb−p143−90 Figure 7–18: Exception Summary Register (ALU_EXC) 3 1 6 5 4 3 2 1 0 Read as Ones 1 Integer Overflow (IOV) Floating Overflow (FOV) Floating Reserved Operand (FRS) Floating Divide by Zero (FDZ) Floating Underflow (FUN) msb−p144−90 Vector Module Registers 7–13
Figure 7–19: Diagnostic Control Register (ALU_DIAG_CTL) 3 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Read as Ones 1 Illegal Favor Opcode (IFO) C−Bus Parity Error (CPE) AB−Bus Parity Error (ABE) Invert Internally Generated C−Bus Parity (ICI) Invert CD−Bus Parity High (ICH) Invert CD−Bus Parity Low (ICL) Invert B Operand Parity High (IBH) Invert B Operand Parity Low (IBL) Invert Scalar Operand Parity High (ISH) Invert Scalar Operand Parity Low (ISL) msb−p145−90 Figure 7–20: Current ALU Instruction Register (VCTL_CALU
Figure 7–21: Deferred ALU Instruction Register (VCTL_DALU) 3 1 2 2 2 4 3 2 Opcode 1 1 1 1 1 1 6 5 4 3 2 1 0 Vector Length 8 7 4 3 0 0 Masked Operations Enable (MOE) Match True/False (MTF) Exception Enable (EXC) or Modify Intent (MI) Vector Register A (VRA) Vector Register B (VRB) Vector Register C (VRC) msb−p146−90 Figure 7–22: Current ALU Operand Low Register (VCTL_COP_LOW) 3 1 0 Scalar Operand Low msb−p147−90 Figure 7–23: Current ALU Operand High Register (VCTL_COP_HI) 3 1 0 Scalar Operand H
Figure 7–24: Deferred ALU Operand Low Register (VCTL_DOP_LOW) 3 1 0 Scalar Operand Low msb−p147−90 Figure 7–25: Deferred ALU Operand High Register (VCTL_DOP_HI) 3 1 0 Scalar Operand High msb−p148−90 7–16 VAX 6000 Model 500 Mini-Reference
Figure 7–26: Load/Store Instruction Register (VCTL_LDST) 6 3 3 2 Load Store Base Address 3 1 2 2 2 4 3 2 Opcode 1 1 1 1 1 1 6 5 4 3 2 1 8 7 4 3 0 Vector Length Modify Intent (MI) Masked Operations Enable (MOE) Match True/False (MTF) Current Processor Mode (CUR MOD) Vector Register A (VRA) Vector Register B (VRB) Vector Register C (VRC) msb−p149−90 Figure 7–27: Load/Store Stride Register (VCTL_STRIDE) 3 1 0 Load/Store Stride msb−p150−90 Vector Module Registers 7–17
Figure 7–28: Illegal Instruction (VCTL_ILL) 3 1 2 2 2 4 3 2 Opcode 1 1 1 1 1 1 6 5 4 3 2 1 0 Vector Length 8 7 4 3 0 0 Masked Operations Enable (MOE) Match True/False (MTF) Exception Enable (EXC) or Modify Intent (MI) Vector Register A (VRA) Vector Register B (VRB) Vector Register C (VRC) msb−p146−90 7–18 VAX 6000 Model 500 Mini-Reference
Figure 7–29: Vector Controller Status (VCTL_CSR) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 0 0 0 1 1 1 1 1 2 1 0 9 8 7 6 5 4 3 2 1 0 MBZ 1 0 Load/Store Chip Soft Error (LSS) Load/Store Chip Hard Error (LSH) Soft Internal Bus Parity Error (CDS) Hard Internal Bus Parity Error (CDH) VIB−Bus Soft Error (VIS) VIB−Bus Hard Error (VIH) Illegal Sequence Error (ISE) Machine Check Code (MCC) Seft−Test Failed (STF) Extended Test Failed (ETF) Verse Hard Error (VHE) Soft Error Enable (SEE)
Figure 7–30: Module Revision (MOD_REV) 3 1 1 1 2 1 8 7 6 Must Be Zero 0 0 VECTL Chip Revision (VECTL REV) Module Revision (MOD REV) msb−p174−90 Figure 7–31: P0 Base Register (LSX_P0BR) 3 3 2 1 0 9 0 9 8 Vector Copy −− P0 Base Register 0 MUST BE ZERO msb−p129−90 Figure 7–32: P0 Length Register (LSX_P0LR) 3 1 2 2 2 1 MUST BE ZERO 0 Vector Copy −− P0 Length Register msb−p130−90 7–20 VAX 6000 Model 500 Mini-Reference
Figure 7–33: P1 Base Register (LSX_P1BR) 3 3 2 1 0 9 0 9 8 Vector Copy −− P1 Base Register 0 MUST BE ZERO msb−p131−90 Figure 7–34: P1 Length Register (LSX_P1LR) 3 1 2 2 2 1 MUST BE ZERO 0 Vector Copy −− P1 Length Register msb−p132−90 Figure 7–35: System Base Register (LSX_SBR) 3 3 2 1 0 9 0 9 8 Vector Copy −− System Base Address 0 MUST BE ZERO msb−p133−90 Vector Module Registers 7–21
Figure 7–36: System Length Register (LSX_SLR) 3 1 2 2 2 1 MUST BE ZERO 0 Vector Copy −− System Length Register msb−p134−90 Figure 7–37: Load/Store Exception Register (LSX_EXC) 3 1 9 8 7 6 0 VA<31:9> of Faulting Reference Fault Type (FT) Exception Code (ECODE) msb−p302−90 Figure 7–38: Translation Buffer Control Register (LSX_TBCSR) 3 3 1 0 2 1 0 MUST BE ZERO Modify Exception Enable (MEE) Diagnostic Mode Enable (DME) Memory Management Enable (MME) msb−p303−90 7–22 VAX 6000 Model 500 Mini-Reference
Figure 7–39: Memory Management Enable (LSX_MAPEN) 3 1 0 Memory Management Enable Register (A Pseudo Register) msb−p135−90 Figure 7–40: Translation Buffer Invalidate All Register (LSX_TBIA) 3 1 0 Translation Buffer Invalidate All msb−p136−90 Figure 7–41: Translation Buffer Invalidate Single Register (LSX_TBIS) 3 1 0 Translation Buffer Invalidate Single msb−p137−90 Vector Module Registers 7–23
Figure 7–42: Vector Mask Low Register (LSX_MASKLO) 3 1 0 Vector Mask Low Register msb−p304−90 Figure 7–43: Vector Mask High Register (LSX_MASKHI) 3 1 0 Vector Mask High Register msb−p305−90 Figure 7–44: Load/Store Stride Register (LSX_STRIDE) 3 1 0 Load/Store Stride Register msb−p306−90 7–24 VAX 6000 Model 500 Mini-Reference
Figure 7–45: Load/Store Instruction Register (LSX_INST) 6 3 3 2 Base Address 3 3 1 0 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 0 MUST BE ZERO Valid Bit (V) Current CPU Mode (CUR MOD) Mask Operate Enable (MOE) Match True/False (MTF) Offset Control (OFF) Address Generation Mode (AGM) Load or Store (LS) Data Length (LQ) Vector Length (VL) msb−p307−90 Vector Module Registers 7–25
Figure 7–46: Cache Control Register (LSX_CCSR) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 0 1 1 1 2 1 0 9 8 5 4 1 0 0 Memory Activity (ACT) Load/Store Chip Revision Node ID (LSXREV) Cache Parity Error (CPE) XMI Interface Soft Error (XSE) XMI Interface Hard Error (XHE) Cache Error Enable (CEE) Soft Error Enable (SEE) Cache Enable (ENA) Cache Hit (HIT) Force Hit (FHT) Flush Cache (FLU) Force Bad Low RFA Parity (FRL) Force Bad Low Data Parity (FDL) Force Bad High Data Parity
Figure 7–48: 6 6 3 2 Translation Buffer PTE Register (LSX_PTE) 5 5 5 9 8 7 5 5 3 2 3 2 Page Frame Number (PFN) Software Bits (SOFT) Modify Bit (M) Protection Field (PROT) Valid Bit (V) 3 3 1 0 2 2 2 7 6 5 2 2 1 0 0 Page Frame Number (PFN) Software Bits (SOFT) Modify Bit (M) Protection Field (PROT) Valid Bit (V) msb−p310−90 Vector Module Registers 7–27
7.
Figure 7–50: FV64A Hard Error Interrupt Parse Tree (select all) (Unrecoverable VIB error) (select one) VINTSR <4> VECTL detected VIB hard error <6> VINTSR C−chip detected VIB hard error VINTSR <7> Scalar DAL bus timeout error VINTSR <8> Vector module is being reset VINTSR <2> (Unrecoverable vector hard error) VPSR <24> (Vector hardware error) (select one) VCTL_CSR <3> CD bus hard error VCTL_CSR <6> Illegal seq
Figure (select 7–51: all)FV64A Soft Error Interrupt Parse Tree (Recoverable VIB error) (select one) VINTSR <3> VECTL detected VIB soft error VINTSR <5> C−chip detected VIB soft error VINTSR (select one) <1> (Recoverable vector error) VCTL_CSR <2> CD bus soft error VCTL_CSR <0> (select all) Load/Store Chip Soft Error LSX_CCSR <10> XMI interface soft error LSX_CCSR <9> Data cache parity error No error bits set Hard error interrupt
Figure 7–52: FV64A Disable Fault Parse Tree VPSR <0> = 0, Vector disabled (select one) VPSR <25> Illegal vector opcode VPSR <7> Vector arithmetic exception (select all) VAER <0> Floating Underflow VAER <1> Floating Divide by Zero VAER <2> Floating Reserved Operand VAER <3> Floating Overflow VAER <5> Integer Overflow No error bits set Hard error interrupt msb−p290−90 Vector Module Registers 7–31
7–32 VAX 6000 Model 500 Mini-Reference
Index A ABEAR, 6–10 Accelerator Control and Status Register, 4–10, 7–7 Access to registers, 7–1 ACCS, 4–10 ACCS register, 7–7 ACSR, 6–9 ADG1, 6–8 AESR, 6–6 AIMR, 6–7 AIVINTR, 6–7 ALU_DIAG_CTL register, 7–14 ALU_EXC register, 7–13 ALU_MASK_HI register, 7–13 ALU_MASK_LO register, 7–12 ALU_OP register, 7–11 ALU_SCOP_HI register, 7–12 ALU_SCOP_LO register, 7–12 AREAR, 6–5 Arithmetic Exception Register, 7–11 ARVR, 6–9 AUTLR, 6–8 B Backup Cache Control Register, 4–13 Backup Cache Deallocate Tag Register, 4–14 Ba
C Cache Control Register, 7–26 Console error messages, 1–11 to 1–21 Console commands SHOW CONFIGURATION and self-test results, 2–5 summary chart, 1–4 Console commands and qualifiers, 1–4 to 1–7 Console control characters, 1–7 Console Receive Data Buffer Register, 4–8 Console Receiver Control and Status Register, 4–8 Console Saved Processor Status Longword, 4–10 Console Saved Program Counter Register, 4–10 Console Transmitter Control and Status Register, 4–9 Console Transmitter Data Buffer Register, 4–9 Cont
Failing Address Extension Register 0, 4–33 Failing Address Register, 4–32, 6–5 Failing DAL Register 0, 4–27 Failing DAL Register 1, 4–27 Failing DAL Register 2, 4–28 Failing DAL Register 3, 4–28 FDAL0, 4–27 FDAL1, 4–27 FDAL2, 4–28 FDAL3, 4–28 First Part Done (FPD) bit, 4–37 FPD (First Part Done) bit, 4–37 H Hard error interrupt parse tree FV64A, 7–29 KA65A, 4–46 to 4–48 I I/O Reset Register, 4–11 I/O space, 3–2, 3–3 I-box, 4–40 ICCS, 4–8 Illegal Instruction Register, 7–18 Implied Vector Interrupt Destinat
MCTL3, 5–8 MCTL4, 5–8 MECEA, 5–4 MECER, 5–4 Memory Control Register 1, 5–3 Memory Control Register 2, 5–5 Memory Control Register 3, 5–8 Memory Control Register 4, 5–8 Memory ECC Error Address Register, 5–4 Memory ECC Error Register, 5–4 Memory Management Enable Register, 7–23 Module Revision Register, 7–20 MOD_REV register, 7–20 /M qualifier, 7–1 MSSC Bus Timeout Control Register, 4–21 MSSC Configuration Register, 4–21 MSSC Input Port Register, 4–22 MSSC Interval Counter Register, 4–26 MSSC Output Port Reg
Self-test (Cont.
VCTL_DOP_LOW register, 7–16 VCTL_ILL register, 7–18 VCTL_LDST register, 7–17 VCTL_STRIDE register, 7–17 Vector Arithmetic Exception Register, 7–8 Vector Controller Status Register, 7–19 Vector Count Register, 7–1 Vector Indirect Address Register, 7–9 Vector Indirect Data High Register, 7–10 Vector Indirect Data Low Register, 7–10 Vector indirect registers, 7–11 to 7–27 Vector Interface Error Status Register, 4–15, 7–7 Vector Length Register, 7–1 Vector Mask High Register, 7–13, 7–24 Vector Mask Low Register
