Specifications
7.0.10
FIBRE
OPTICS
ELECTRICAL LOOP-BACK
The
Fibre
Control
Register
is
set
for
Electrical
Loop-
Back
Mode,
and
two
checkerboard
patterns
($5555
and
SAAAA)
are
then
written
to
the
Host
Control
and
Status
Re~ister
individually.
After
writing
each
pattern,
NXM
is
checked
for
error
status
on
the
packet.
If
NXM
is
oka~,
then
the
pattern
is
read
back
from
the
loop-back
address.
If
the
packet
returns
bad
information,
the
data
will
be
either
all
ones
or
all
zeroes.
Followin~
this
test,
the
Fibre
Control
Register
is
set
for
Powerup
State
and
Link_Available
is
checked.
If
the
host's
fibre
light
is
on,
the
Link_Available
software
flag
is
set
and
the
terminal's
fibre
lisht
is
set
at
the
end
of
Powerup
(provided
that
a
Link
Transition
interrupt
is
not
received
in
the
meantime).
Otherwise,
the
terminal's
fibre
lisht
remains
off
until
a
Link
Transition
interrupt
occurs.
An~
time
the
Fibre
Control
Re~ister
is
written
to,
it
must
be
followed
b~
a
1ms
timer
to
allow
the
host
time
to
receive
the
new
status.
7.0.11
VSYNC
VECTOR
TIMEOUT
Interrupt
are
now
enabled.
If
we
do
not
receive
a
vs~nc interru~t
within
lOOms,
a
failure
is
reported.
7.0.12
FRAME
BUFFER
MEMORY
The
same
scheme
is
used
as
in
the
ProSram
Memor~
test;
thou~h
frame
buffer
memor~
is
tested
in
four
Guadrants,
for
the
sake
of
speed
and
modularit~.
Each
Guadrant
of
frame
buffer
memor~
is
the
same
size
as
proSram
memor~,
so
the
frame
buffer
test
entails
four
calls
to
the
common
memor~
test.
7.0.13
BIT-BLOCK TRANSFER
ACCELERATOR
MODULE
The
VS100
status
resister
is
checked
for
th~
presence
of
the
BBA.
If
the
BBA
is
present,
four
tests
are
executed:
1.
Scratchpad
RAM
--
all
256
words
2.
Cop~area
3.
Halftones
4.
Vectors