Technical data

System Dump Analyzer
SHOW CPU
• Stack pointers and memory interconnect silos
The first section includes registers that maintain the virtual address space,
system space, or other system functions of the current process. The following
registers are among those displayed:
Register Description
P0BR Program region (P0 space) base register
P0LR Program region length register
P1BR Control region (P1 space) base register
P1LR Control region length register
SBR System region (S0 space) base register
SLR System region length register
PCBB Process control block base register
SCBB System control block base register
ASTLVL Asynchronous system trap level
SISR Software interrupt summary register
ICCS Internal clock control and status register
SID System identification register
The second section of the processor registers display shows those registers
that are specific to the type of processor being examined. (The SHOW CRASH
command displays the processor type.) The contents of the register display vary
according to the type of processor involved in the crash and are used primarily in
hardware diagnostics.
The final section of the display includes the five stack pointers: the interrupt
stack pointer (ISP) and the four pointers of the kernel, executive, supervisor, and
user stacks (KSP, ESP, SSP, and USP, respectively). Certain processors, such as
the VAX 8800 and VAX 8600 processors, also display the contents of the silos of
their memory interconnects in this section.
The SHOW CPU command concludes with a listing of the spin locks, if any, owned
by the processor at the time of the crash, reproducing some of the information
given by the SHOW SPINLOCKS command. The spin lock display includes the
following information:
• Name of the spin lock.
• Address of the spin lock data structure (SPL).
• IPL and rank of the spin lock.
• Number of processors waiting for this processor to release the spin lock.
• Indication of the depth of this processor’s ownership of the spin lock. A
number greater than 1 indicates that this processor has nested acquisitions of
the spin lock.
SDA–95